Nonvolatile memories in spiking neural network architectures: Current and emerging trends

ML Varshika, F Corradi, A Das - Electronics, 2022 - mdpi.com
A sustainable computing scenario demands more energy-efficient processors.
Neuromorphic systems mimic biological functions by employing spiking neural networks for …

Device-aware test: A new test approach towards DPPB level

M Fieback, L Wu, GC Medeiros, H Aziza… - 2019 IEEE …, 2019 - ieeexplore.ieee.org
This paper proposes a new test approach that goes beyond cell-aware test, ie, device-aware
test. The approach consists of three steps: defect modeling, fault modeling, and test/DfT …

Defects, fault modeling, and test development framework for RRAMs

M Fieback, GC Medeiros, L Wu, H Aziza… - ACM Journal on …, 2022 - dl.acm.org
Resistive RAM (RRAM) is a promising technology to replace traditional technologies such
as Flash, because of its low energy consumption, CMOS compatibility, and high density …

Defect and fault modeling framework for STT-MRAM testing

L Wu, S Rao, M Taouil, GC Medeiros… - … on Emerging Topics …, 2019 - ieeexplore.ieee.org
STT-MRAM mass production is around the corner as major foundries worldwide invest
heavily on its commercialization. To ensure high-quality STT-MRAM products, effective yet …

Smart Hammering: A practical method of pinhole detection in MRAM memories

SB Mamaghani, C Münch, J Yun… - … , Automation & Test …, 2023 - ieeexplore.ieee.org
As we move toward the commercialization of Spin-Transfer Torque Magnetic Random
Access Memories (STT-MRAM), cost-effective testing and in-field reliability have become …

Pinhole defect characterization and fault modeling for STT-MRAM testing

L Wu, S Rao, GC Medeiros, M Taouil… - 2019 IEEE European …, 2019 - ieeexplore.ieee.org
The STT-MRAM manufacturing process involves not only traditional CMOS process steps,
but also the integration of magnetic tunnel junction (MTJ) devices, the data-storing elements …

Testing resistive memories: Where are we and what is missing?

M Fieback, M Taouil, S Hamdioui - 2018 IEEE International Test …, 2018 - ieeexplore.ieee.org
Resistive RAM (RRAM) is one of the emerging non-volatile memories that may not only
replace DRAM and/or Flash in the future, but also enable new computing paradigms such as …

Testing computation-in-memory architectures based on emerging memories

S Hamdioui, M Fieback, S Nagarajan… - … IEEE International Test …, 2019 - ieeexplore.ieee.org
Today's computing architectures and device technologies are incapable of meeting the
increasingly stringent demands on energy and performance posed by evolving applications …

Defect characterization and test generation for spintronic-based compute-in-memory

SM Nair, C Münch, MB Tahoori - 2020 IEEE European Test …, 2020 - ieeexplore.ieee.org
Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM), as one of the most
promising emerging memory technology for on-chip memory, offers many advantageous …

Survey on STT-MRAM testing: Failure mechanisms, fault models, and tests

L Wu, M Taouil, S Rao, EJ Marinissen… - arXiv preprint arXiv …, 2020 - arxiv.org
As one of the most promising emerging non-volatile memory (NVM) technologies, spin-
transfer torque magnetic random access memory (STT-MRAM) has attracted significant …