Ramp-based biasing in a memory device

H Giduturi - US Patent 11,205,480, 2021 - Google Patents
Methods and systems include memory devices with multiple access lines arranged in an
array to form a multiple inter sections. Memory cells are located at the intersections of the …

Memory apparatus and method of operation using state bit-scan dependent ramp rate for peak current reduction during program operation

YC Lien, HL Hsu, HY Tseng, F Zhang - US Patent 11,521,686, 2022 - Google Patents
(57) ABSTRACT A memory apparatus and method of operation is provided. The apparatus
includes memory cells connected to word lines and bit lines and configured to retain a …

Multi-stage voltage control for peak and average current reduction of open blocks

YC Lien, HY Tseng, D Dutta - US Patent 11,189,337, 2021 - Google Patents
Aspects of a storage device including a memory and a controller are provided which allow
for reduction of current in open blocks during read operations using multi-stage read voltage …

Memory cells for storing operational data

M Boniardi, AM Conti, I Tortorelli - US Patent 11,417,398, 2022 - Google Patents
Methods, systems, and devices for memory cells for storing operational data are described.
A memory device may include an array of memory cells with different sets of cells for storing …

Efficient read of NAND with read disturb mitigation

YC Lien, T Eliash, HY Tseng - US Patent 11,600,343, 2023 - Google Patents
(JJC J/(%(200601) mitigate read disturb. The read spike and channel clean each H ()//,
27///582 (201701) take a significant amount of time to perform. However, since H () …

Memory cells for storing operational data

M Boniardi, AM Conti, I Tortorelli - US Patent 11,783,897, 2023 - Google Patents
Methods, systems, and devices for memory cells for storing operational data are described.
A memory device may include an array of memory cells with different sets of cells for storing …

Balancing peak power with programming speed in non-volatile memory

T Razzak, J Yuan, D Dutta - US Patent 11,961,563, 2024 - Google Patents
Technology is disclosed herein for a memory system that balances peak Icc with
programming speed. A memory system applies voltages to respective word lines during a …

Memory apparatus and method of operation using plane dependent ramp rate and timing control for program operation

YC Lien, HY Tseng, T Eliash - US Patent 11,386,968, 2022 - Google Patents
A memory apparatus and method of operation is provided. The apparatus includes memory
cells connected to word lines and bit lines and arranged in a plurality of planes. The …

Power reduction during open and erased block reads of memory based on the position of last written word line of a memory block

N Lu, N Yang - US Patent 11,521,688, 2022 - Google Patents
(57) ABSTRACT A data storage device including, in one implementation, a non-volatile
memory and a controller. The non-volatile memory includes a memory block. The memory …

Ramp-based biasing and adjusting of access line voltage in a memory device

H Giduturi - US Patent 11,769,552, 2023 - Google Patents
Methods and systems include memory devices with multiple access lines arranged in an
array to form a multiple intersections. Memory cells are located at the intersections of the …