Survey on Redundancy Based-Fault tolerance methods for Processors and Hardware accelerators-Trends in Quantum Computing, Heterogeneous Systems and …
S Venkatesha, R Parthasarathi - ACM Computing Surveys, 2024 - dl.acm.org
Rapid progress in the CMOS technology for the past 25 years has increased the
vulnerability of processors towards faults. Subsequently, focus of computer architects shifted …
vulnerability of processors towards faults. Subsequently, focus of computer architects shifted …
[PDF][PDF] Read-Write Dependency Aware Register Allocation.
S Xiao, Y Chen, J He, X Yang - Comput. Syst. Sci. Eng., 2023 - cdn.techscience.cn
Read-write dependency is an important factor restricting software efficiency. Timing
Speculative (TS) is a processing architecture aiming to improve energy efficiency of …
Speculative (TS) is a processing architecture aiming to improve energy efficiency of …
A Survey of fault mitigation techniques for multi-core architectures
S Venkatesha, R Parthasarathi - arXiv preprint arXiv:2112.14952, 2021 - arxiv.org
Fault tolerance in multi-core architecture has attracted attention of research community for
the past 20 years. Rapid improvements in the CMOS technology resulted in exponential …
the past 20 years. Rapid improvements in the CMOS technology resulted in exponential …
异构多核的一种高性能容错调度方法与仿真
余世干， 唐志敏， 叶笑春， 张志敏 - 系统仿真学报, 2018 - china-simulation.com
针对TMR (Three mode redundancy) 在解决处理器瞬态故障时存在性能低下, 功耗较高等问题,
提出了一种考虑容错的面向异构多核的调度方法TEAHFT, 把任务划分为敏感性任务和具有容错 …
提出了一种考虑容错的面向异构多核的调度方法TEAHFT, 把任务划分为敏感性任务和具有容错 …
High Performance Fault-tolerant Scheduling Method and Simulation for Heterogeneous Multicore
S Yu, Z Tang, X Ye, Z Zhang - Journal of …, 2019 - dc-china-simulation …
To deal with the problem of low performance and high power consumption when solving the
transient fault of the processor with three mode redundancy (TMR), a task execution …
transient fault of the processor with three mode redundancy (TMR), a task execution …
Extended prefix including routing bit for extended instruction format
GR Frazier, HQ Le - US Patent 11,119,777, 2021 - Google Patents
Techniques for an extended prefix including a routing bit for an extended instruction format
are described herein. An aspect includes generating, by an instruction preprocessing …
are described herein. An aspect includes generating, by an instruction preprocessing …