Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures

L Alvarez, L Vilanova, M Moreto, M Casas… - Proceedings of the …, 2015 - dl.acm.org
The increasing number of cores in manycore architectures causes important power and
scalability problems in the memory subsystem. One solution is to introduce scratchpad …

Runtime-aware architectures: A first approach

M Valero, M Moreto, M Casas, E Ayguade… - … frontiers and innovations, 2014 - superfri.org
In the last few years, the traditional ways to keep the increase of hardware performance at
the rate predicted by Moore's Law have vanished. When uni-cores were the norm, hardware …

Runtime-guided management of scratchpad memories in multicore architectures

L Alvarez, M Moretó, M Casas, E Castillo… - 2015 International …, 2015 - ieeexplore.ieee.org
The increasing number of cores and the anticipated level of heterogeneity in upcoming
multicore architectures cause important problems in traditional cache hierarchies. A good …

Partitioning and Data Mapping in Reconfigurable Cache and Scratchpad Memory--Based Architectures

P Chakraborty, PR Panda, S Sen - ACM Transactions on Design …, 2016 - dl.acm.org
Scratchpad memory (SPM) is considered a useful component in the memory hierarchy,
solely or along with caches, for meeting the power and energy constraints as performance …

Design and implementation of cache coherence protocol for high-speed multiprocessor system

DP Kaur, V Sulochana - 2018 2nd IEEE International …, 2018 - ieeexplore.ieee.org
To maintain data consistency between the cache memories in centralized and distributed
shared-memory multiprocessor system, particular protocols are used known as cache …

Defect classification algorithm for IC photomask based on PCA and SVM

S Chen, T Hu, G Liu, Z Pu, M Li… - 2008 Congress on Image …, 2008 - ieeexplore.ieee.org
During IC photomask vision inspection, considering problem that fine image defectpsilas
fineness, complex shape, extraction feature difficultly, and effect by noise easily, presented …

A survey of hardware and software co-design issues for system on chip design

J Kokila, N Ramasubramanian, S Indrajeet - Advanced Computing and …, 2016 - Springer
The modern embedded system needs to be designed to meet the tremendous changes due
to high speed and advancement in technologies. Encapsulating user needs into a small …

Rmem: An os service for transparent remote memory access in lightweight manycores

PH Penna, M Souza, EP Junior, J Souto… - MultiProg 2019-25th …, 2019 - hal.science
Lightweight manycores deliver high performance and scal-ability at low power consumption.
However, architectural intricacies of these processors impose programmability challenges …

Local memory store (LMStr): A hardware controlled shared scratchpad for multicores

NA Siddique, AHA Badawy, J Cook… - 2017 IEEE SmartWorld …, 2017 - ieeexplore.ieee.org
We present an on-chip memory store called “Local Memory Store”(LMStr). The LMStr can be
used with a regular cache hierarchy or solely as a redesigned scratchpad memory (SPM) …

SAM: software-assisted memory hierarchy for scalable manycore embedded systems

M Shoushtari, N Dutt - IEEE Embedded Systems Letters, 2017 - ieeexplore.ieee.org
This letter proposes a system architecture for a scalable software-assisted memory (SAM)
hierarchy for emerging manycore embedded systems. Our SAM hierarchy overcomes the …