Xpipes: A network-on-chip architecture for gigascale systems-on-chip
D Bertozzi, L Benini - IEEE circuits and systems magazine, 2004 - ieeexplore.ieee.org
The growing complexity of embedded multiprocessor architectures for digital media
processing will soon require highly scalable communication infrastructures. Packet switched …
processing will soon require highly scalable communication infrastructures. Packet switched …
System-on-chip: Reuse and integration
Over the past ten years, as integrated circuits became increasingly more complex and
expensive, the industry began to embrace new design and reuse methodologies that are …
expensive, the industry began to embrace new design and reuse methodologies that are …
Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip
E Rijpkema, K Goossens, A Rădulescu, J Dielissen… - … -Computers and Digital …, 2003 - IET
Managing the complexity of designing chips containing billions of transistors requires
decoupling computation from communication. For the communication, scalable and …
decoupling computation from communication. For the communication, scalable and …
System-scenario-based design of dynamic embedded systems
SV Gheorghita, M Palkovic, J Hamers… - ACM Transactions on …, 2009 - dl.acm.org
In the past decade, real-time embedded systems have become much more complex due to
the introduction of a lot of new functionality in one application, and due to running multiple …
the introduction of a lot of new functionality in one application, and due to running multiple …
An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration
A Radulescu, J Dielissen, SG Pestana… - … on computer-aided …, 2004 - ieeexplore.ieee.org
We present a network interface (NI) for an on-chip network. Our NI decouples computation
from communication by offering a shared-memory abstraction, which is independent of the …
from communication by offering a shared-memory abstraction, which is independent of the …
A design flow for application-specific networks on chip with guaranteed performance to accelerate SOC design and verification
K Goossens, J Dielissen, OP Gangwal… - … Automation and Test …, 2005 - ieeexplore.ieee.org
Systems on chip (SOC) are composed of intellectual property blocks (IP) and interconnect.
While mature tooling exists to design the former, tooling for interconnect design is still a …
While mature tooling exists to design the former, tooling for interconnect design is still a …
Survey on real-time networks-on-chip
Multi-Processor Systems-on-Chip (MPSoCs) have emerged as an evolution trend to meet
the growing complexity of embedded applications with increasing computation parallelism …
the growing complexity of embedded applications with increasing computation parallelism …
Virtual channels in networks on chip: implementation and evaluation on hermes NoC
Networks on chip (NoCs) draw on concepts inherited from distributed systems and computer
networks subject areas to interconnect IP cores in a structured and scalable way …
networks subject areas to interconnect IP cores in a structured and scalable way …
Systematic and automated multiprocessor system design, programming, and implementation
H Nikolov, T Stefanov… - IEEE Transactions on …, 2008 - ieeexplore.ieee.org
For modern embedded systems in the realm of high-throughput multimedia, imaging, and
signal processing, the complexity of embedded applications has reached a point where the …
signal processing, the complexity of embedded applications has reached a point where the …
The ACROSS MPSoC–A new generation of multi-core processors designed for safety–critical embedded systems
C El Salloum, M Elshuber, O Höftberger… - Microprocessors and …, 2013 - Elsevier
Abstract The European ARTEMIS ACROSS project aims to overcome the limitations of
existing Multi-Processor Systems-on-a-Chip (MPSoC) architectures with respect to safety …
existing Multi-Processor Systems-on-a-Chip (MPSoC) architectures with respect to safety …