IntAct: A 96-core processor with six chiplets 3D-stacked on an active interposer with distributed interconnects and integrated power management

P Vivet, E Guthmuller, Y Thonnart… - IEEE Journal of Solid …, 2020 - ieeexplore.ieee.org
In the context of high-performance computing, the integration of more computing capabilities
with generic cores or dedicated accelerators for artificial intelligence (AI) application is …

2.3 a 220gops 96-core processor with 6 chiplets 3d-stacked on an active interposer offering 0.6 ns/mm latency, 3tb/s/mm 2 inter-chiplet interconnects and 156mw/mm …

P Vivet, E Guthmuller, Y Thonnart… - … Solid-State Circuits …, 2020 - ieeexplore.ieee.org
In the context of high-performance computing and big-data applications, the quest for
performance requires modular, scalable, energy-efficient, low-cost manycore systems …

Active interposer technology for chiplet-based advanced 3D system architectures

P Coudrain, J Charbonnier, A Garnier… - 2019 IEEE 69th …, 2019 - ieeexplore.ieee.org
We report the first successful technology integration of chiplets on an active silicon
interposer, fully processed, packaged and tested. Benefits of chiplet-based architectures are …

PROWAVES: Proactive runtime wavelength selection for energy-efficient photonic NoCs

A Narayan, Y Thonnart, P Vivet… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
2.5-D manycore systems running parallel applications are severely bottlenecked by network-
on-chip (NoC) latencies and bandwidth. Traditionally, NoCs are composed of electrical links …

WAVES: Wavelength selection for power-efficient 2.5 D-integrated photonic NoCs

A Narayan, Y Thonnart, P Vivet… - … , Automation & Test …, 2019 - ieeexplore.ieee.org
Photonic Network-on-Chips (PNoCs) offer promising benefits over Electrical Network-on-
Chips (ENoCs) in many-core systems owing to their lower latencies, higher bandwidth, and …

[PDF][PDF] by 3 MRRs at the Rx site.

TIA TIA - drive.google.com
Fig. 1. An example silicon-photonic link. An off-chip laser emits 3 optical signals that are
modulated by 3 MRRs at the Tx site and filtered by 3 MRRs at the Rx site. control loop to …

[PDF][PDF] Model-Based System Design for Chiplet-Based Architectures

DDCEA List - chipletsummit.com
Model-Based System Design for Chiplet-Based Architectures Page 1 Model-Based System
Design for Chiplet-Based Architectures Denis Dutoit – CEA List Program Manager – Advanced …