In a processor, a thread agnostic unified store queue and a unified load queue method for
out of order loads in a memory consistency model using shared memory resources. The …

In a processor, a disambiguation-free out of order load store queue method. The method
includes implementing a memory resource that can be accessed by a plurality of …

An out of order processor. The processor includes a virtual load store queue for allocating a
plurality of loads and a plurality of stores, wherein more loads and more stores can be …

In a processor, a lock-based method for out of order loads in a memory consistency model
using shared memory resources. The method includes implementing a memory resource …

An out of order processor. The processor includes a distributed load queue and a distributed
store queue that maintain single program sequential semantics while allowing an out of …

In a processor, a disambiguation-free out of order load store queue method. The method
includes implementing a memory resource that can be accessed by a plurality of …

A method for forwarding data from the store instructions to a corresponding load instruction
in an out of order processor. The method includes accessing an incoming sequence of …

In a processor, a method for using a semaphore with out of order loads in a memory
consistency model that constitutes loads reading from memory in order. The method …

A method for forwarding data from the store instructions to a corresponding load instruction
in an out of order processor. The method includes accessing an incoming sequence of …

In a processor, a method for filtering stores to prevent all stores from having to Snoop check
against all words of a cache. The method includes implementing a cache wherein stores …