Clock distribution networks synchronize the flow of data signals among synchronous data
paths. The design of these networks can dramatically affect system-wide performance and …

Clock distribution networks synchronize the flow of data signals between data paths, and the
design of these networks can dramatically affect system wide performance and reliability …

Over the years, the fundamentals of VLSI technology have evolved to include a wide range
of topics and a broad range of practices. To encompass such a vast amount of knowledge …

Presenting a comprehensive overview of the design automation algorithms, tools, and
methodologies used to design integrated circuits, the Electronic Design Automation for …

In this article, we propose new approaches for solving the useful-skew tree (UST) routing
problem [Xi and Dai 1997]: clock routing subject to general skew constraints. The clock …

Embedded computer systems use both off-the-shelf microprocessors and application-
specific integrated circuits (ASICs) to implement specialized system functions. Examples …

A methodology is presented in this paper for determining an optimal set of clock path delays
for designing high performance VLSI/ULSI-based clock distribution networks. This …

The author considers the problem of optimizing the parameters of a multiphase clock for a
circuit containing both edge-triggered flip-flops and level-sensitive latches. He demonstrates …

High speed synchronous digital systems require large switching currents to facilitate rapid
signal transitions. These large currents create voltage drops on the power distribution …

Min-max functions, F: R n R n, arise in modelling the dynamic behaviour of discrete event
systems. They form a dense subset of those functions which are homogeneous, F i (x 1+ h …