A survey of architectural techniques for managing process variation
S Mittal - ACM Computing Surveys (CSUR), 2016 - dl.acm.org
Process variation—deviation in parameters from their nominal specifications—threatens to
slow down and even pause technological scaling, and mitigation of it is the way to continue …
slow down and even pause technological scaling, and mitigation of it is the way to continue …
Building robust machine learning systems: Current progress, research challenges, and opportunities
Machine learning, in particular deep learning, is being used in almost all the aspects of life
to facilitate humans, specifically in mobile and Internet of Things (IoT)-based applications …
to facilitate humans, specifically in mobile and Internet of Things (IoT)-based applications …
Towards energy-efficient and secure edge AI: A cross-layer framework ICCAD special session paper
The security and privacy concerns along with the amount of data that is required to be
processed on regular basis has pushed processing to the edge of the computing systems …
processed on regular basis has pushed processing to the edge of the computing systems …
Fault-tolerant systolic array based accelerators for deep neural network execution
Editor's note: Systolic array is embracing its renaissance after being accepted by Google
TPU as the core computing architecture of machine learning acceleration. In this article, the …
TPU as the core computing architecture of machine learning acceleration. In this article, the …
TSP: Thermal safe power: Efficient power budgeting for many-core systems in dark silicon
Chip manufacturers provide the Thermal Design Power (TDP) for a specific chip. The
cooling solution is designed to dissipate this power level. But because TDP is not …
cooling solution is designed to dissipate this power level. But because TDP is not …
Thermal safe power (TSP): Efficient power budgeting for heterogeneous manycore systems in dark silicon
Chip manufacturers provide the Thermal Design Power (TDP) for a specific chip. The
cooling solution is designed to dissipate this power level. But because TDP is not …
cooling solution is designed to dissipate this power level. But because TDP is not …
DRVS: Power-efficient reliability management through dynamic redundancy and voltage scaling under variations
Many-core processors facilitate coarse-grained reliability by exploiting available cores for
redundant multithreading. However, ensuring high reliability with reduced power …
redundant multithreading. However, ensuring high reliability with reduced power …
Computing in the dark silicon era: Current trends and research challenges
M Shafique, S Garg - IEEE Design & Test, 2016 - ieeexplore.ieee.org
Computing in the Dark Silicon Era: Current Trends and Research Challenges Page 1 2168-2356
(c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE …
(c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE …
Multi-layer dependability: From microarchitecture to application level
We show in this paper that multi-layer dependability is an indispensable way to cope with
the increasing amount of technology-induced dependability problems that threaten to …
the increasing amount of technology-induced dependability problems that threaten to …
Dark silicon as a challenge for hardware/software co-design: Invited special session paper
Dark Silicon refers to the observation that in future technology nodes, it may only be possible
to power-on a fraction of on-chip resources (processing cores, hardware accelerators, cache …
to power-on a fraction of on-chip resources (processing cores, hardware accelerators, cache …