Turbo codes and the iterative algorithm for decoding them sparked a new era in the theory
and practice of error control codes. Turbo equalization followed as a natural extension to this …

We present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by
utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) …

Three low-power Viterbi decoder (VD) architectures are presented in this paper. In the first,
limited decision errors are introduced in the add-compare-select units (ACSUs) of a VD to …

Most of advanced wireless standards, such as WiMAX and LTE, have adopted different
convolutional turbo code (CTC) schemes with various block sizes and throughput rates …

In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless
systems. To support various 4G standards, a configurable multi-mode MAP (maximum a …

Low-density parity-check (LDPC) codes and convolutional Turbo codes are two of the most
powerful error correcting codes that are widely used in modern communication systems. In a …

Memristor has emerged as one of the most promising candidates for the fundamental device
in the beyond-CMOS era. With their unique advantage on implementing low-power high …

Presented in this paper is a pipelined 285-MHz maximum a posteriori probability (MAP)
decoder IC. The 8.7-mm/sup 2/IC is implemented in a 1.8-V 0.18-/spl mu/m CMOS …

Implementation of an efficient turbo decoder with low complexity, short delay and
insignificant performance degradation is currently a quite challenging task. The paper …

Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two
of the most powerful error correction codes known to perform very close to the Shannon limit …