HERMES: an infrastructure for low area overhead packet-switching networks on chip
The increasing complexity of integrated circuits drives the research of new on-chip
interconnection architectures. A network on chip draws on concepts inherited from …
interconnection architectures. A network on chip draws on concepts inherited from …
Classroom makerspaces: Identifying the opportunities and challenges
This paper aims at introducing, identifying opportunities, presenting a vision and stakeholder
driven challenges regarding the concept of classroom makerspaces. With the engineering …
driven challenges regarding the concept of classroom makerspaces. With the engineering …
Network-on-chip design and synthesis outlook
With the growing complexity in consumer embedded products, new tendencies forecast
heterogeneous Multi-Processor Systems-On-Chip (MPSoCs) consisting of complex …
heterogeneous Multi-Processor Systems-On-Chip (MPSoCs) consisting of complex …
Dynoc: A dynamic infrastructure for communication in dynamically reconfugurable devices
A new paradigm to support the communication among modules dynamically placed on a
reconfigurable device at run-time is presented. Based on the network on chip (NoC) …
reconfigurable device at run-time is presented. Based on the network on chip (NoC) …
An FPGA run-time system for dynamical on-demand reconfiguration
M Ullmann, M Hübner, B Grimm… - … Parallel and Distributed …, 2004 - ieeexplore.ieee.org
Summary form only given. The handling of an increasing number of automotive comfort
functionalities has become a significant problem for the most automobile manufacturers …
functionalities has become a significant problem for the most automobile manufacturers …
Fast, accurate and detailed NoC simulations
PT Wolkotte, PKF Holzenspies… - … Symposium on Networks …, 2007 - ieeexplore.ieee.org
Network-on-chip (NoC) architectures have a wide variety of parameters that can be adapted
to the designer's requirements. Fast exploration of this parameter space is only possible at a …
to the designer's requirements. Fast exploration of this parameter space is only possible at a …
Operating-system controlled network on chip
V Nollet, T Marescaux, D Verkest, JY Mignolet… - Proceedings of the 41st …, 2004 - dl.acm.org
Managing a Network-on-Chip (NoC) in an efficient way is a challenging task. To succeed,
the operating system (OS) needs to be tuned to the capabilities and the needs of the NoC …
the operating system (OS) needs to be tuned to the capabilities and the needs of the NoC …
Parallel hardware hypervisor for virtualizing application-specific supercomputers
7. B-1 (P1) sends message to Bo (not mapped) Cache miss handled by owner P3 containing
A1 is chosen for pre-empting Ownero asks owner to undo (A1-) P3) map (A1-) P3) entry in …
A1 is chosen for pre-empting Ownero asks owner to undo (A1-) P3) map (A1-) P3) entry in …
Dynamic interconnection of reconfigurable modules on reconfigurable devices
C Bobda, A Ahmadinia - IEEE Design & Test of Computers, 2005 - ieeexplore.ieee.org
This article presents two approaches to solving the problem of communication between
components dynamically placed at runtime on a reconfigurable device. The first is a circuit …
components dynamically placed at runtime on a reconfigurable device. The first is a circuit …
Topology adaptive network-on-chip design and implementation
TA Bartic, JY Mignolet, V Nollet, T Marescaux… - … -Computers and Digital …, 2005 - IET
Network-on-chip designs promise to offer considerable advantages over the traditional bus-
based designs in solving the numerous technological, economic and productivity problems …
based designs in solving the numerous technological, economic and productivity problems …