Muchisim: A simulation framework for design exploration of multi-chip manycore systems
The design space exploration of scaled-out manycores for communication-intensive
applications (eg, graph analytics and sparse linear algebra) is hampered due to either lack …
applications (eg, graph analytics and sparse linear algebra) is hampered due to either lack …
CIFER: A Cache-Coherent 12nm 16mm2 SoC With Four 64-Bit RISC-V Application Cores, 18 32-Bit RISC-V Compute Cores, and a 1541 LUT6/mm2 Synthesizable …
This letter presents CIFER, the world's first open-source, fully cache-coherent,
heterogeneous many-core, CPU-FPGA system-on-chips. The 12 nm, 16-mm2 chip …
heterogeneous many-core, CPU-FPGA system-on-chips. The 12 nm, 16-mm2 chip …
Dynamic Resource Management in Reconfigurable SoC for Multi-Tenancy Support
This study introduces a partially reconfigurable system-on-chip (SoC) platform leveraging
dynamic resource management facilitated by a dynamic reconfigurable control processor …
dynamic resource management facilitated by a dynamic reconfigurable control processor …
SLMLET: A RISC-V Processor SoC with Tightly-Coupled Area-Efficient eFPGA Blocks
SLMLET is a low-power System-on-a-Chip (SoC), which is a promising device for edge
computing. It consists of a RISC-V core and area-saving embedded Field-programmable …
computing. It consists of a RISC-V core and area-saving embedded Field-programmable …