A low clock power data-gated flip-flop is provided. The data-gated flip-flop includes an
exclusive OR component including a first exclusive OR input, a second exclusive OR input …

A low-power synchronizer circuit, a data processing circuit that incorporates the
synchronizer circuit, and a synchronization method are provided. The synchronizer circuit …

A method and an apparatus for wireless communication are provided. The apparatus having
a first latch having a first latch input and first latch output and a second latch having a second …

US9746877B2 - Detecting and correcting an error in a digital circuit - Google Patents
US9746877B2 - Detecting and correcting an error in a digital circuit - Google Patents Detecting …

In one embodiment, a clock-gating system for a pipeline includes a clock-gating device
configured to gate or pass a clock signal to the pipeline, and a clock controller. The clock …

An apparatus includes a latch of a clock gating circuit (CGC). The latch is configured to
generate a first signal in response to a clock signal. The apparatus further includes a delay …

Disclosed herein are embodiments related to a power efficient multi-bit storage system. In
one configuration, the multi-bit storage system includes a first storage circuit, a second …