Code density concerns for new architectures
Reducing a program's instruction count can improve cache behavior and bandwidth
utilization, lower power consumption, and increase overall performance. Nonetheless, code …
utilization, lower power consumption, and increase overall performance. Nonetheless, code …
Code compression for VLIW embedded systems using a self-generating table
We propose a new class of methods for VLIW code compression using variable-sized
branch blocks with self-generating tables. Code compression traditionally works on fixed …
branch blocks with self-generating tables. Code compression traditionally works on fixed …
Code Compression in ARM Embedded Systems using Multiple Dictionaries
This paper presents a new code compression method where we use different dictionaries,
all of them are based in traditional Huffman algorithm. Our method reduces code size by up …
all of them are based in traditional Huffman algorithm. Our method reduces code size by up …
Dual code compression for embedded systems
K Shrivastava, P Mishra - 2011 24th internatioal conference on …, 2011 - ieeexplore.ieee.org
Computer architects aim to make embedded systems more powerful and space efficient.
Code compression is traditionally used to reduce the code size by compressing the …
Code compression is traditionally used to reduce the code size by compressing the …
[PDF][PDF] Reduce static code size and improve RISC-V compression
P Li - 2019 - escholarship.org
Embedded systems are ubiquitous and indispensable from our daily life today. In contrast to
traditional programs that are given large size of memory, embedded applications-such as …
traditional programs that are given large size of memory, embedded applications-such as …
Sparc16: A new compression approach for the sparc architecture
RISC processors can be used to face the ever increasing demand for performance required
by embedded systems. Nevertheless, this solution comes with the cost of poor code density …
by embedded systems. Nevertheless, this solution comes with the cost of poor code density …
Design of a Decompressor Engine on a SPARC Processor
E Billo, R Azevedo, G Araujo, P Centoducatte… - Proceedings of the 18th …, 2005 - dl.acm.org
Code compression, initially conceived as an effective technique to reduce code size in
embedded systems, today also brings advantages in terms of performance and energy …
embedded systems, today also brings advantages in terms of performance and energy …
A power-aware code-compression design for RISC/VLIW architecture
CW Lin, CH Lin, WJ Wang - Journal of Zhejiang University SCIENCE C, 2011 - Springer
We studied the architecture of embedded computing systems from the viewpoint of power
consumption in memory systems and used a selective-code-compression (SCC) approach …
consumption in memory systems and used a selective-code-compression (SCC) approach …
An Approach for Code Compression in Run Time for Embedded Systems–A Preliminary Results
Several factors are considered in the development of embedded systems, among which may
be mentioned: physical size, weight, mobility, power consumption, memory, safety, all …
be mentioned: physical size, weight, mobility, power consumption, memory, safety, all …
[PDF][PDF] Using dynamic binary instrumentation to create faster, validated, multi-core simulations
V Weaver - 2010 - ecommons.cornell.edu
The Memory Wall continues to be a problem with modern systems design. While the steady
increase in processor speeds has abated somewhat, Moore's Law continues to provide …
increase in processor speeds has abated somewhat, Moore's Law continues to provide …