Furion: Engineering high-quality immersive virtual reality on today's mobile devices
In this paper, we perform a systematic design study of the" elephant in the room" facing the
VR industry--is it feasible to enable high-quality VR apps on untethered mobile devices such …
VR industry--is it feasible to enable high-quality VR apps on untethered mobile devices such …
Parallel scalability of video decoders
C Meenderinck, A Azevedo, B Juurlink… - Journal of Signal …, 2009 - Springer
An important question is whether emerging and future applications exhibit sufficient
parallelism, in particular thread-level parallelism, to exploit the large numbers of cores future …
parallelism, in particular thread-level parallelism, to exploit the large numbers of cores future …
Task mapping on SMART NoC: Contention matters, not the distance
On-chip communication is the bottleneck of system performance for NoC-based MPSoCs.
SMART, a recently proposed NoC architecture, enables single-cycle multi-hop …
SMART, a recently proposed NoC architecture, enables single-cycle multi-hop …
Application mapping and scheduling for network-on-chip-based multiprocessor system-on-chip with fine-grain communication optimization
Network-on-chip (NoC) is promising for the communication paradigm of the next-generation
multiprocessor system-on-chip (MPSoC). As communication has become an integral part of …
multiprocessor system-on-chip (MPSoC). As communication has become an integral part of …
Satisfiability modulo graph theory for task mapping and scheduling on multiprocessor systems
Task graph scheduling on multiprocessor systems is a representative multiprocessor
scheduling problem. A solution to this problem consists of the mapping of tasks to …
scheduling problem. A solution to this problem consists of the mapping of tasks to …
FoToNoC: A folded torus-like network-on-chip based many-core systems-on-chip in the dark silicon era
Dark silicon refers to the phenomenon that a fraction of a many-core chip has to become
“dark” or “dim” in order to guarantee the system to be kept in a safe temperature range and …
“dark” or “dim” in order to guarantee the system to be kept in a safe temperature range and …
Image decoding apparatus and image coding apparatus wth parallel decoding
Y Hayashi, H Amano, M Iguchi - US Patent 9,042,457, 2015 - Google Patents
An image decoding apparatus which decodes, in parallel, a coded stream having
processing order dependency includes: a slice data predecoding unit which predecodes, on …
processing order dependency includes: a slice data predecoding unit which predecodes, on …
Scalability of macroblock-level parallelism for h. 264 decoding
This paper investigates the scalability of MacroBlock (MB) level parallelization of the H. 264
decoder for High Definition (HD) applications. The study includes three parts. First, a formal …
decoder for High Definition (HD) applications. The study includes three parts. First, a formal …
Parallelization of H. 264 video decoder for embedded multicore processor
K Nishihara, A Hatabu… - 2008 IEEE international …, 2008 - ieeexplore.ieee.org
This paper presents two parallelization methods for H. 264 video decoder software on an
embedded multicore processor. In parallelizing the H. 264 video decoder software on a …
embedded multicore processor. In parallelizing the H. 264 video decoder software on a …
VCMaker: Content-aware configuration adaptation for video streaming and analysis in live augmented reality
The emergence of edge computing has enabled mobile Augmented Reality (AR) on edge
servers. We notice that the video configurations, ie, frames per second (fps) and resolution …
servers. We notice that the video configurations, ie, frames per second (fps) and resolution …