The data partitioning and scheduling strategies used by DNN accelerators to leverage reuse
and perform staging are known as dataflow, which directly impacts the performance and …

Moving data through the memory hierarchy is a fundamental bottleneck that can limit the
performance of core algorithms of machine learning, such as convolutional neural networks …

A spatial accelerator's efficiency depends heavily on both its mapper and cost models to
generate optimized mappings for various operators of DNN models. However, existing cost …

In this paper we introduce a multi-objective autotuning framework comprising compiler and
runtime components. Focusing on individual code regions, our compiler uses a novel search …

Code transformations, such as loop tiling and loop fusion, are of key importance for the
efficient implementation of stencil computations. However, their direct application to a large …

Optimizing compilers implement program transformation strategies aimed at reducing data
movement to or from main memory by exploiting the data-cache hierarchy. However, instead …

Tiling is a key technique to reduce data movement in matrix computations. While tiling is well
understood and widely used for dense matrix/tensor computations, effective tiling of sparse …

Data movement between processor and memory hierarchy is a fundamental bottleneck that
limits the performance of many applications on modern computer architectures. Tiling and …

A desirable feature of a development tool for SoC design is that, given the important
applications in the domain to be targeted by the SoC, a powerful hardware-software …

Loop tiling is a widely used loop transformation to enhance data locality and allow data
reuse. In the tiled code, however, tiles of different sizes can lead to significant variation in …