Low voltage analog circuit design techniques: A tutorial

S Yan, E Sanchez-Sinencio - IEICE Transactions on Fundamentals …, 2000 - search.ieice.org
Low voltage (LV) analog circuit design techniques are addressed in this tutorial. In
particular,(i) technology considerations;(ii) transistor model capable to provide performance …

Analog integrated circuits design for processing physiological signals

Y Li, CCY Poon, YT Zhang - IEEE Reviews in Biomedical …, 2010 - ieeexplore.ieee.org
Analog integrated circuits (ICs) designed for processing physiological signals are important
building blocks of wearable and implantable medical devices used for health monitoring or …

A 128128 1.5% Contrast Sensitivity 0.9% FPN 3 µs Latency 4 mW Asynchronous Frame-Free Dynamic Vision Sensor Using Transimpedance Preamplifiers

T Serrano-Gotarredona… - IEEE Journal of Solid …, 2013 - ieeexplore.ieee.org
Dynamic Vision Sensors (DVS) have recently appeared as a new paradigm for vision
sensing and processing. They feature unique characteristics such as contrast coding under …

Tradeoffs and optimization in analog CMOS design

DM Binkley - 2007 14th International Conference on Mixed …, 2007 - ieeexplore.ieee.org
The selection of drain current, inversion coefficient, and channel length for each MOS device
in an analog circuit results in significant tradeoffs in performance. The selection of inversion …

An ultra-low-voltage ultra-low-power CMOS Miller OTA with rail-to-rail input/output swing

LHC Ferreira, TC Pimenta… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
An ultra-low-voltage ultra-low-power CMOS Miller operational transconductance amplifier
(OTA) with rail-to-rail input/output swing is presented. The topology is based on combining …

[图书][B] The gm/ID Methodology, a sizing tool for low-voltage analog CMOS Circuits: The semi-empirical and compact model approaches

P Jespers - 2009 - books.google.com
IC designers appraise currently MOS transistor geometries and currents to compromise
objectives like gain-bandwidth, slew-rate, dynamic range, noise, non-linear distortion, etc …

A 2-nW 1.1-V self-biased current reference in CMOS technology

EM Camacho-Galeano… - … on Circuits and …, 2005 - ieeexplore.ieee.org
This work presents the design of an ultra-low-power self-biased 400-pA current source. We
propose the use of a very simple topology along with a design methodology based on the …

[图书][B] MOSFET modeling for circuit analysis and design

C Galup-Montoro - 2007 - books.google.com
This is the first book dedicated to the next generation of MOSFET models. Addressed to
circuit designers with an in-depth treatment that appeals to device specialists, the book …

An MOS transistor model for RF IC design valid in all regions of operation

C Enz - IEEE Transactions on Microwave Theory and …, 2002 - ieeexplore.ieee.org
This paper presents an overview of MOS transistor modeling for RF integrated circuit design.
It starts with the description of a physical equivalent circuit that can easily be implemented as …

Nanowatt, sub-nS OTAs, with sub-10-mV input offset, using series-parallel current mirrors

A Arnaud, R Fiorelli… - IEEE Journal of Solid …, 2006 - ieeexplore.ieee.org
In this paper, series-parallel (SP) current-division will be employed for the design of very low
transconductance OTAs. From the theory and measurements, it will be shown that SP …