We consider the problem of reasoning with linear temporal logic on truncated paths. A
truncated path is a path that is finite, but not necessarily maximal. Truncated paths arise …

We present a technique for generating efficient monitors for ω-regular-languages. We show
how Büchi automata can be reduced in size and transformed into special, statistically …

In this book we present a number of techniques leading to the automated generation of
checker circuits from modern hardware assertion languages. Today, verification takes over …

This paper presents an effective approach to formally verify SystemC designs. The approach
translates SystemC models into a Petri-Net based representation. The Petri-net model is …

Assertion-based verification (ABV) is emerging as a paramount technique for industrial-
strength hardware verification, especially through the emerging property specification …

Faced with the steadily increasing complexity and rapidly shortening timeto-market
requirements designing electronic systems is a very challenging task. To manage this …

We describe a toolbox for the analysis of Systems-on-a-chip written in SystemC at the
transaction level. The tool is able to extract information from SystemC code, and to build a …

Rietveld refinements of the structure of calcined ALPO4-5 have been performed using
synchrotron and neutron powder diffraction data. The high-resolution synchrotron X-ray …

In this work we study hybrid approaches to LTL symbolic model checking; that is,
approaches that use explicit representations of the property automaton, whose state space …

With ever increasing design sizes, verification becomes the bottleneck in modem design
flows. Up to 80% of the overall costs are due to the verification task. Formal methods have …