A 1D-CNN based deep learning technique for sleep apnea detection in IoT sensors
Internet of Things (IoT) enabled wearable sensors for health monitoring are widely used to
reduce the cost of personal healthcare and improve quality of life. The sleep apnea …
reduce the cost of personal healthcare and improve quality of life. The sleep apnea …
A 0.05 mm², 350 mv, 14 nw fully-integrated temperature sensor in 180-nm cmos
In this brief, we present a fully-integrated ring-oscillator based CMOS temperature sensor for
Internet-of-Things. Our design relies on a low-complexity PMOS-based sensing circuit to …
Internet-of-Things. Our design relies on a low-complexity PMOS-based sensing circuit to …
Multimodal multiresolution data fusion using convolutional neural networks for IoT wearable sensing
With advances in circuit design and sensing technology, the acquisition of data from a large
number of Internet of Things (IoT) sensors simultaneously to enable more accurate …
number of Internet of Things (IoT) sensors simultaneously to enable more accurate …
Sub-nW microcontroller with dual-mode logic and self-startup for battery-indifferent sensor nodes
In this article, a battery-indifferent microcontroller unit (MCU) with wide power-performance
scaling is presented to enable continuous operation with a sub-mm 2 on-chip solar cell …
scaling is presented to enable continuous operation with a sub-mm 2 on-chip solar cell …
SomnNET: An SpO2 based deep learning network for sleep apnea detection in smartwatches
The abnormal pause or rate reduction in breathing is known as the sleep-apnea hypopnea
syndrome and affects the quality of sleep of an individual. A novel method for the detection …
syndrome and affects the quality of sleep of an individual. A novel method for the detection …
An 8 bit 12.4 TOPS/W phase-domain MAC circuit for energy-constrained deep learning accelerators
Y Toyama, K Yoshioka, K Ban, S Maya… - IEEE Journal of Solid …, 2019 - ieeexplore.ieee.org
A small-gate-count 8 bit bidirectional phase-domain MAC (PMAC) circuit is proposed to
minimize both area and energy consumption of extremely energy-efficient deep neural …
minimize both area and energy consumption of extremely energy-efficient deep neural …
All-analog silicon integration of image sensor and neural computing engine for image classification
We have designed a fully-integrated analog CMOS cognitive image sensor based on a two-
layer artificial neural network and targeted to low-resolution image classification. We have …
layer artificial neural network and targeted to low-resolution image classification. We have …
A 0.8-V, 1.54-pJ/940-MHz dual-mode logic-based 16× 16-b booth multiplier in 16-nm FinFET
The dual-mode logic (DML) defines runtime adapted digital architectures that switch to either
improved performance or lower energy consumption as a function of the actual …
improved performance or lower energy consumption as a function of the actual …
Programmable All-in-One 4x8-/2x16-/1x32-bits Dual Mode Logic Multiplier in 16 nm FinFET with Semi-Automatic Flow
In this paper, an improved multiplier architecture, utilizing dual mode logic (DML) targeting
single-instruction-multiple-data (SIMD)-like systems is proposed. The design introduces …
single-instruction-multiple-data (SIMD)-like systems is proposed. The design introduces …
Binary classifiers for data integrity detection in wearable IoT edge devices
This paper presents a comparison of several artificial intelligence (AI) based binary
classifiers for detecting the integrity of data obtained from Internet of Things (IoT) enabled …
classifiers for detecting the integrity of data obtained from Internet of Things (IoT) enabled …