Emerging monolithic 3D integration: Opportunities and challenges from the computer system perspective

Y Cheng, X Guo, VF Pavlidis - Integration, 2022 - Elsevier
In the past decade, monolithic three dimensional integrated circuits (M3D-ICs) advance fast
and demonstrate several important breakthroughs in the fabrication process and circuit level …

Advances in design and test of monolithic 3-D ICs

A Chaudhuri, S Banerjee, H Park, J Kim… - IEEE Design & …, 2020 - ieeexplore.ieee.org
Monolithic 3-D (M3D) technology enables unprecedented degrees of integration on a single
chip. The miniscule monolithic intertier vias (MIVs) in M3D are the key behind higher …

Quantifying the benefits of monolithic 3D computing systems enabled by TFT and RRAM

AM Felfel, K Datta, A Dutt, H Veluri… - … , Automation & Test …, 2020 - ieeexplore.ieee.org
Current data-centric workloads, such as deep learning, expose the memory-access
inefficiencies of current computing systems. Monolithic 3D integration can overcome this …

Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits

T Srimani, RM Radway, J Kim, K Prabhu… - … , Automation & Test …, 2023 - ieeexplore.ieee.org
This paper focuses on iso-on-chip-memory-capacity and iso-footprint Energy-Delay-Product
(EDP) benefits of ultra-dense 3D, eg, monolithic 3D (M3D), computing systems vs …

NodeRank: Observation-point insertion for fault localization in monolithic 3D ICs

A Chaudhuri, S Banerjee… - 2020 IEEE 29th Asian …, 2020 - ieeexplore.ieee.org
Monolithic 3D (M3D) ICs have emerged as a promising technology with significant
improvement in power, performance, and area (PPA) over conventional 3D-stacked ICs …

Merging PDKs to build a design environment for 3D circuits: methodology, challenges and limitations

O Billoint, K Azizi-Mourier, G Cibrario… - 2019 International …, 2019 - ieeexplore.ieee.org
Design of 3D ICs is mainly done in separated design environments for each tier, assuming
that communication channels between tiers are user-defined and fixed at the beginning of …

Multi-tier 3D IC physical design with analytical quadratic partitioning algorithm using 2D P&R tool

A Tamir, M Salem, J Lin, Q Alasad, J Yuan - Electronics, 2021 - mdpi.com
In this study, we developed a complete flow for the design of monolithic 3D ICs. We have
taken the register-transfer level netlist of a circuit as the input and synthesized it to construct …

A ReRAM memory compiler for monolithic 3D integrated circuits in a carbon nanotube process

E Lee, D Kim, J Kim, SK Lim… - ACM Journal on Emerging …, 2021 - dl.acm.org
We present a ReRAM memory compiler for monolithic 3D (M3D) integrated circuits (IC). We
develop ReRAM architectures for M3D ICs using 1T-1R bit cells and single and multiple tiers …

Area and Power Optimized RTL to GDS II Flow of a Telecommunication Receiver Core

K Jayasurya, R Ajith… - 2024 5th International …, 2024 - ieeexplore.ieee.org
The Register Transfer Level (RTL) to Graphic Design System II (GDS II) flow is pivotal in any
integrated circuit (IC) design. The work outlines the process of IC design from RTL to GDS II …

A test response compression method for monolithic 3-D ICs based on 3-D haar wavelet transforms

J Hu, Y Lin, M Hu, H Wang - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
This article presents an advanced method for monolithic 3-D integrated circuits (ICs)'test
compression based on 3-D Haar wavelet transforms. The main purpose of this study is to …