A 130nm CMOS Programmable Analog Standard Cell Library

J Hasler, PR Ayyappan, A Ige… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
This work presents an experimentally measured, implemented, openly-available
programmable analog standard cell library in Skywater's 130nm CMOS process …

An All-Digital, 1.92–7.32 mV/LSB, 0.5–2 GS/s Sample Rate, and 0-Latency Prediction Voltage Sensor With Dynamic PVT Calibration for Droop Detection and AVS …

Y Du, J Qian, Z Chen, W Shan - IEEE Transactions on Circuits …, 2023 - ieeexplore.ieee.org
The on-chip droop in processor may cause a severe voltage reduction resulting in a need for
high-speed and high-resolution on-chip voltage sensors. However, traditional voltage …

A Capacitorless External-Clock-Free Fully-Synthesizable Digital LDO with Time-Based Load-State Decision and Asynchronous Recovery

J Oh, Y Song, YH Hwang, JE Park… - … on Power Electronics, 2023 - ieeexplore.ieee.org
This article presents an external-clock-free fully synthesizable digital low-dropout regulator
(DLDO) without an output capacitor. To lower quiescent current in a steady state, time-based …

A high-load current low-dropout regulator with adaptive ESR compensation

A Wang, X Zhang, W Cheng, H Ren, G Liu… - … -International Journal of …, 2024 - Elsevier
This paper presents a dynamic pseudo equivalent series resistance (DPESR) zero-point
compensation technology applied to high-current high-precision low-dropout (LDO) …

A DVS-Enabled Distributed Digital LDO Providing Rapid Uniform Power Grid and Ripple Reduction Achieving 20.1-ps FOM in 28 nm CMOS

Y Han, J Kim, G Koo, J Kim, J Kim… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
A dynamic voltage scaling (DVS) enabled distributed digital low-dropout voltage regulator
(LDO) is described. The proposed distributed LDO utilizes a multi-point average sensing to …

An Adaptive-Sampling Digital LDO with Statistical Comparator Selection Achieving 99.99% Maximum Current Efficiency and 0.25 ps FoM in 65nm

S Yamaguchi, T Hisakado, O Wada… - 2023 IEEE Asian Solid …, 2023 - ieeexplore.ieee.org
Attention to digital LDO has been increasing due to their low-power and wide-voltage-range
operation. For fine-grain power control of an SoC (System-on-a-Chip), LDOs with small …

A 2.5-A 3-ns-Response-Time Calibration-Free Hybrid LDO Using Scalable Self-Clocked Stochastic Flash-ADC for In-Loop Quantization

T Lyu, Z Wang, J Guo - … Transactions on Circuits and Systems I …, 2024 - ieeexplore.ieee.org
This paper presents a dual-loop hybrid low-dropout regulator (LDO) to resolve the conflicts
between transient response and load capability. At the digital end, a scalable stochastic …

An Output-Capacitor-Free NMOS Digital LDO Using Gate Driving Strength Modulation and Droop Detector

J Kim, G Koo, S Lee, JH Shim… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
An output-capacitor-free NMOS digital LDO (DLDO) using gate driving strength modulation
(GDSM) is described. The proposed DLDO is mainly based on the time-driven topology …

Model-Based Study on the Limit of the Dynamic Load Regulation Performance of a Digital Low Dropout Regulator

Y Xu, Z Wang, J Oh, M Seok - IEEE Transactions on Very Large …, 2024 - ieeexplore.ieee.org
A digital low dropout (DLDO) regulator is one of the most critical building blocks in on-chip
power management for its technology portability, voltage scalability, and other benefits …

An Ultra-Wide Load-Range Fast-Transient Output Capacitor-Less Digital LDO With Adaptive Gate Modulation and Droop Detection

G Koo, J Kim, S Lee, JH Shim… - IEEE Solid-State Circuits …, 2024 - ieeexplore.ieee.org
An ultrawide load-range output capacitor-less digital LDO (DLDO) with an adaptive gate
modulation scheme is described. The proposed DLDO is primarily regulated by digital codes …