The princeton shape benchmark
In recent years, many shape representations and geometric algorithms have been proposed
for matching 3D shapes. Usually, each algorithm is tested on a different (small) database of …
for matching 3D shapes. Usually, each algorithm is tested on a different (small) database of …
Analytical fault tolerance assessment and metrics for TSV-based 3D network-on-chip
Reliability is one of the most challenging problems in the context of three-dimensional
network-on-chip (3D NoC) systems. Reliability analysis is prominent for early stages of the …
network-on-chip (3D NoC) systems. Reliability analysis is prominent for early stages of the …
Security and vulnerability implications of 3D ICs
Physical limit of transistor miniaturization has driven chip design into the third dimension. 3D
integration technology emerges as a viable option to improve chip performance and …
integration technology emerges as a viable option to improve chip performance and …
TSV-based 3-D ICs: Design methods and tools
Vertically integrated circuits (3-D ICs) may revitalize Moore's law scaling which has slowed
down in recent years. 3-D stacking is an emerging technology that stacks multiple dies …
down in recent years. 3-D stacking is an emerging technology that stacks multiple dies …
Low capacitance through-silicon-vias with uniform benzocyclobutene insulation layers
Low capacitance is critical to the electric performance of through-silicon-vias (TSVs). This
paper reports the development of a low capacitance TSVs by replacing silicon dioxide …
paper reports the development of a low capacitance TSVs by replacing silicon dioxide …
Modeling and crosstalk evaluation of 3-D TSV-based inductor with ground TSV shielding
S Mondal, SB Cho, BC Kim - IEEE Transactions on Very Large …, 2016 - ieeexplore.ieee.org
In this paper, we present a novel through-silicon-via (TSV)-based 3-D inductor structure with
ground TSV shielding for better noise performance. In addition, a circuit model is proposed …
ground TSV shielding for better noise performance. In addition, a circuit model is proposed …
Modeling and optimization of multiground TSVs for signals shield in 3-D ICs
C Qu, R Ding, X Liu, Z Zhu - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
This paper presents an effective loop impedance extraction method and a model of a signal
through-silicon via (TSV) surrounded by multiground TSVs. According to this method, the …
through-silicon via (TSV) surrounded by multiground TSVs. According to this method, the …
An enhancement of crosstalk avoidance code based on fibonacci numeral system for through silicon vias
X Cui, X Cui, Y Ni, M Miao… - IEEE Transactions on Very …, 2017 - ieeexplore.ieee.org
Through silicon vias (TSVs) play an important role as the vertical electrical connections in 3-
D stacked integrated circuits. However, the closely clustered TSVs suffer from the crosstalk …
D stacked integrated circuits. However, the closely clustered TSVs suffer from the crosstalk …
Crosstalk avoidance codes for 3D VLSI
R Kumar, SP Khatri - 2013 Design, Automation & Test in …, 2013 - ieeexplore.ieee.org
In 3D VLSI, through-silicon vias (TSVs) are relatively large, and closely spaced. This results
in a situation in which noise on one or more TSVs may deteriorate the delay and signal …
in a situation in which noise on one or more TSVs may deteriorate the delay and signal …
Silicon effect-aware full-chip extraction and mitigation of TSV-to-TSV coupling
This paper presents a silicon effect-aware multiTSV model. Through-silicon-via (TSV)
depletion region, silicon substrate discharging path and electrical field distribution around …
depletion region, silicon substrate discharging path and electrical field distribution around …