Micro/nanoscale 3D assembly by rolling, folding, curving, and buckling approaches
The miniaturization of electronics has been an important topic of study for several decades.
The established roadmaps following Moore's Law have encountered bottlenecks in recent …
The established roadmaps following Moore's Law have encountered bottlenecks in recent …
A review of recent research on heat transfer in three-dimensional integrated circuits (3-D ICs)
Three-dimensional integrated circuits (3-D IC) technology has emerged in the past few
decades, driven in part by the techno-economic difficulties of dimensional scaling and the …
decades, driven in part by the techno-economic difficulties of dimensional scaling and the …
A survey on chip to system reverse engineering
The reverse engineering (RE) of electronic chips and systems can be used with honest and
dishonest intentions. To inhibit RE for those with dishonest intentions (eg, piracy and …
dishonest intentions. To inhibit RE for those with dishonest intentions (eg, piracy and …
GRIM-Filter: Fast seed location filtering in DNA read mapping using processing-in-memory technologies
Background Seed location filtering is critical in DNA read mapping, a process where billions
of DNA fragments (reads) sampled from a donor are mapped onto a reference genome to …
of DNA fragments (reads) sampled from a donor are mapped onto a reference genome to …
A survey of optimization techniques for thermal-aware 3D processors
Interconnect scaling has become a major design challenge for traditional planar (2D)
integrated circuits (ICs). Three-dimensional (3D) IC that stacks multiple device layers …
integrated circuits (ICs). Three-dimensional (3D) IC that stacks multiple device layers …
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC
Three-dimensional integrated circuit (3D IC) with through-silicon-via (TSV) is believed to
offer new levels of efficiency, power, performance, and form-factor advantages over the …
offer new levels of efficiency, power, performance, and form-factor advantages over the …
TSV-aware analytical placement for 3D IC designs
Through-silicon vias (TSVs) are required for transmitting signals among different dies for the
three-dimensional integrated circuit (3D IC) technology. The significant silicon areas …
three-dimensional integrated circuit (3D IC) technology. The significant silicon areas …
A design tradeoff study with monolithic 3D integration
C Liu, SK Lim - Thirteenth International Symposium on Quality …, 2012 - ieeexplore.ieee.org
This paper studies various design tradeoffs existing in the monolithic 3D integration
technology. Different design styles in monolithic 3D ICs are studied, including transistor …
technology. Different design styles in monolithic 3D ICs are studied, including transistor …
SunFloor 3D: A tool for networks on chip topology synthesis for 3-D systems on chips
Three-dimensional integrated circuits (3D-ICs) are a promising approach to address the
integration challenges faced by current systems on chips (SoCs). Designing an efficient …
integration challenges faced by current systems on chips (SoCs). Designing an efficient …
Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC
This paper studies TSV-to-TSV coupling in 3D ICs. A full-chip SI analysis flow is proposed
based on the proposed coupling model. Analysis results show that TSVs cause significant …
based on the proposed coupling model. Analysis results show that TSVs cause significant …