Memory-based PUFs are vulnerable as well: A non-invasive attack against SRAM PUFs

BMSB Talukder, F Ferdaus… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Memory-based physical unclonable functions (mPUFs) are widely accepted as highly
secure because of the unclonable and immutable nature of manufacturer process variations …

A Noninvasive Technique to Detect Authentic/Counterfeit SRAM Chips

BMS Bahar Talukder, F Ferdaus… - ACM Journal on Emerging …, 2023 - dl.acm.org
Many commercially available memory chips are fabricated worldwide in untrusted facilities.
Therefore, a counterfeit memory chip can easily enter into the supply chain in different …

Analysis of Power, Delay and SNM of 6T & 8T SRAM Cells

V Choudhary, DS Yadav - 2021 5th International Conference …, 2021 - ieeexplore.ieee.org
6T and 8T SRAM cells have been compared on 180nm technology using an industry-
standard Cadence Virtuoso Tool. It's challenging to make an SRAM cell with low power …

Low power, high speed VLSI circuits in 16nm technology

S Alluri, B Balaji, C Cury - AIP Conference Proceedings, 2021 - pubs.aip.org
In this paper deals with simulation of FINFET device and subsequent application to a design
of 6 Transistor Static RAM cell with FINFET as well as analysis of design issues and …

CMOS-Based SRAM with Odd-Numbered Transistor Configurations: An Extensive Study

DS Yadav, P Singh, V Choudhary - Advanced Field-Effect …, 2023 - taylorfrancis.com
Researchers working with electrical devices face the challenge of developing products that
have higher functionality while consuming a smaller amount of energy. The widespread use …

CMOS-Based SRAM with Odd-Numbered Transistor Configurations

DS Yadav, P Singh, V Choudhary - Advanced Field-Effect …, 2023 - books.google.com
Researchers working with electronic devices face the challenge of making devices with
greater performance but lower power consumption. Immense usage of electronic products is …

Extraction and Comparative Inspection of several parameters of 6T, 8T, 10T SRAM

RM Gangadari, DS Yadav - 2021 First International Conference …, 2021 - ieeexplore.ieee.org
For good memory design we need to explore the stability of the circuit in read and write
modes and parallely keep track of better read and write delays. The main significance of this …

Analyzing the Low Power Techniques in SRAM Cells at 45nm Node Technology

S Dhariwal, AK Thomas, R Korah… - 2024 IEEE 4th …, 2024 - ieeexplore.ieee.org
This paper presents Gated Vdd and MTCMOS techniques to achieve low power from the
simulated static random-access memory (SRAM) cells. These techniques are implemented …

Design and Analysis of Low Power CMOS SRAM Cells 7T and 9T

V Choudhary, DS Yadav - 2022 10th International Conference …, 2022 - ieeexplore.ieee.org
7T and 9T SRAM cells are compared by the software Cadence Virtuoso tool using 180nm
technology. Designing a memory of low power consumption is a challenging concept in the …

COMPARATIVE ANALYSIS OF LOW POWER SRAM CELLS USING GATED VDD AND MTCMOS TECHNIQUES

S Dhariwal, AK Thomas, R Korah… - International Journal of …, 2023 - search.proquest.com
Abstract In this paper, Gated Vdd and MTCMOS techniques are proposed to get low power
from the simulated SRAM cells considering 4T, 5T and 6T circuits based on CMOS logic. In …