Verification is a serious bottleneck in the industrial hardware design cycle, routinely
requiring person-years of effort. Practical verification relies on a" best effort" process that …

Arithmetic block identification in gate-level netlist is an essential procedure for malicious
logic detection, functional verification, or macro-block optimization. We argue that existing …

Motivated by the recent success of the algebraic computation technique in formal verification
of large and optimized gate-level multipliers, this paper proposes algebraic equivalence …

Trust and security of microelectronic systems are a major driver for game-changing trends
like autonomous driving or the internet of things. These trends are endangered by threats …

Galois field (GF) arithmetic is used to implement critical arithmetic components in
communication and security-related hardware, and verification of such components is of …

Arithmetic block identification in gate-level netlists plays an essential role for various
purposes, including malicious logic detection, functional verification, or macro-block …

Galois field (GF) arithmetic circuits find numerous applications in communications, signal
processing, and security engineering. Formal verification techniques of GF circuits are …

Extracting word-level functions from gate-level circuits is challenging and crucial in security,
synthesis, and verification applications. State-of-the-art approaches identify subcircuits to …

Manual RTL design and optimization remains prevalent across the semiconductor industry
because commercial logic and high-level synthesis tools are unable to match human …

Bit-vector formulas arising from hardware verification problems often contain word-level
arithmetic operations. Empirical evidence shows that state-of-the-art SMT solvers are not …