Power reduction techniques for microprocessor systems
V Venkatachalam, M Franz - ACM Computing Surveys (CSUR), 2005 - dl.acm.org
Power consumption is a major factor that limits the performance of computers. We survey the
“state of the art” in techniques that reduce the total power consumed by a microprocessor …
“state of the art” in techniques that reduce the total power consumed by a microprocessor …
Recent thermal management techniques for microprocessors
Microprocessor design has recently encountered many constraints such as power, energy,
reliability, and temperature. Among these challenging issues, temperature-related issues …
reliability, and temperature. Among these challenging issues, temperature-related issues …
High performance cache replacement using re-reference interval prediction (RRIP)
A Jaleel, KB Theobald, SC Steely Jr… - ACM SIGARCH computer …, 2010 - dl.acm.org
Practical cache replacement policies attempt to emulate optimal replacement by predicting
the re-reference interval of a cache block. The commonly used LRU replacement policy …
the re-reference interval of a cache block. The commonly used LRU replacement policy …
Leakage current: Moore's law meets static power
Off-state leakage is static power, current that leaks through transistors even when they are
turned off. The other source of power dissipation in today's microprocessors, dynamic power …
turned off. The other source of power dissipation in today's microprocessors, dynamic power …
[图书][B] Memory systems: cache, DRAM, disk
B Jacob, D Wang, S Ng - 2010 - books.google.com
Is your memory hierarchy stopping your microprocessor from performing at the high level it
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …
should be? Memory Systems: Cache, DRAM, Disk shows you how to resolve this problem …
Adaptive insertion policies for high performance caching
MK Qureshi, A Jaleel, YN Patt, SC Steely… - ACM SIGARCH …, 2007 - dl.acm.org
The commonly used LRU replacement policy is susceptible to thrashing for memory-
intensive workloads that have a working set greater than the available cache size. For such …
intensive workloads that have a working set greater than the available cache size. For such …
Drowsy caches: simple techniques for reducing leakage power
On-chip caches represent a sizable fraction of the total power consumption of
microprocessors. Although large caches can significantly improve performance, they have …
microprocessors. Although large caches can significantly improve performance, they have …
SHiP: Signature-based hit predictor for high performance caching
The shared last-level caches in CMPs play an important role in improving application
performance and reducing off-chip memory bandwidth requirements. In order to use LLCs …
performance and reducing off-chip memory bandwidth requirements. In order to use LLCs …
Cache revive: Architecting volatile STT-RAM caches for enhanced performance in CMPs
High density, low leakage and non-volatility are the attractive features of Spin-Transfer-
Torque-RAM (STT-RAM), which has made it a strong competitor against SRAM as a …
Torque-RAM (STT-RAM), which has made it a strong competitor against SRAM as a …
Microarchitectural techniques for power gating of execution units
Z Hu, A Buyuktosunoglu, V Srinivasan… - Proceedings of the …, 2004 - dl.acm.org
Leakage power is a major concern in current and future microprocessor designs. In this
paper, we explore the potential of architectural techniques to reduce leakage through power …
paper, we explore the potential of architectural techniques to reduce leakage through power …