A 0.5 V 1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS
A Shikata, R Sekimoto, T Kuroda… - IEEE Journal of Solid …, 2012 - ieeexplore.ieee.org
This paper presents an extremely low-voltage operation and power efficient successive-
approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is …
approximation-register (SAR) analog-to-digital converter (ADC). Tri-level comparator is …
An energy-efficient low frequency-dependence switching technique for SAR ADCs
This brief presents a highly energy-efficient switching scheme for successive approximation
register (SAR) analog-to-digital converters that achieves a 95% reduction in switching …
register (SAR) analog-to-digital converters that achieves a 95% reduction in switching …
A 0.5-V 5.2-fJ/conversion-step full asynchronous SAR ADC with leakage power reduction down to 650 pW by boosted self-power gating in 40-nm CMOS
R Sekimoto, A Shikata, K Yoshioka… - IEEE Journal of Solid …, 2013 - ieeexplore.ieee.org
This paper presents an ultralow-power and ultralow-voltage SAR ADC. Full asynchronous
operation and boosted self-power gating are proposed to improve conversion accuracy and …
operation and boosted self-power gating are proposed to improve conversion accuracy and …
A 250-MS/s 9.9-ENOB 80.7 dB-SFDR Top-Plate Input SAR ADC With Charge Linearization
This brief presents a linearity enhancement method, named charge linearization technique
(CLT), for top-plate input successive approximation register (SAR) data converters. The …
(CLT), for top-plate input successive approximation register (SAR) data converters. The …
A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications
This paper presents a 9-bit 25 kS/s SAR ADC in 0.18 μm CMOS technology for neural signal
recording applications. The ADC is powered by a single supply voltage of 1V to comply with …
recording applications. The ADC is powered by a single supply voltage of 1V to comply with …
A 0.5 V 16nW 8.08-ENOB SAR ADC for ultra-low power sensor applications
This paper presents an ASIC design of ultra-low power SAR ADC. To achieve ultra-low
power, the proposed ADC operates at ultra-low voltage, deploying a single-ended structure …
power, the proposed ADC operates at ultra-low voltage, deploying a single-ended structure …
A 40nm CMOS full asynchronous nano-watt SAR ADC with 98% leakage power reduction by boosted self power gating
R Sekimoto, A Shikata, K Yoshioka… - 2012 IEEE Asian …, 2012 - ieeexplore.ieee.org
This paper presents an ultra low power and ultra low voltage SAR ADC. Full asynchronous
operation and boosted self power gating are proposed to improve conversion accuracy and …
operation and boosted self power gating are proposed to improve conversion accuracy and …
A compact 10-bit nonbinary weighted switched capacitor integrator based SAR ADC architecture
A compact switched capacitor integrator (SCI) based successive approximation register
(SAR) analog to digital converter (ADC) for data acquisition system is presented. This …
(SAR) analog to digital converter (ADC) for data acquisition system is presented. This …
Clock-less 8-bit SAR-ADC with delay-line based digital control circuit
M Borgarino, L Giacomini, G Luppi, F Digiaro… - Microelectronics …, 2019 - Elsevier
Aim of the present paper is to propose an 8 bit SAR-ADC architecture where no external
clock signals or on-chip clock generation circuits are used. The digital control circuitry is …
clock signals or on-chip clock generation circuits are used. The digital control circuitry is …
[PDF][PDF] A low voltage low power 10-Bit successive approximation ADC for remote geriatric care applications
ML Sheu, LJ Tsao, CY Sueh, TH Liu - International Journal of …, 2012 - researchgate.net
A low voltage and low power 10-bit SAR ADC for remote geriatric care applications is
proposed. The SAR ADC employs top-plate sampling architecture with multi-layer sandwich …
proposed. The SAR ADC employs top-plate sampling architecture with multi-layer sandwich …