A DPD/Dither-Free DPLL Based on a Cascaded Fractional Divider and Pseudo-Differential DTCs Achieving a 62.1-dBc Fractional Spur
This article presents a 7-GHz fractional-N digital phase-locked loop (DPLL) without any
digital pre-distortion (DPD) on the integral nonlinearity (INL) of the digital-to-time converter …
digital pre-distortion (DPD) on the integral nonlinearity (INL) of the digital-to-time converter …
Digital Phase-Locked Loops: Exploring Different Boundaries
This article examines the research area of digital phase-locked loops (DPLLs), a critical
component in modern electronic systems, from wireless communication devices to RADAR …
component in modern electronic systems, from wireless communication devices to RADAR …
Calibration of parametric error of digital-to-time converters
MH Perrott - US Patent 11,632,116, 2023 - Google Patents
US11632116B2 - Calibration of parametric error of digital-to-time converters - Google
Patents US11632116B2 - Calibration of parametric error of digital-to-time converters …
Patents US11632116B2 - Calibration of parametric error of digital-to-time converters …
Low power digital-to-time converter (DTC) linearization
US11632230B2 - Low power digital-to-time converter (DTC) linearization - Google Patents
US11632230B2 - Low power digital-to-time converter (DTC) linearization - Google Patents …
US11632230B2 - Low power digital-to-time converter (DTC) linearization - Google Patents …
Type-I PLLs for phase-controlled applications
M Perin, S Dal Toso, K Waheed, CG Rey - US Patent 11,545,982, 2023 - Google Patents
(Continued) Primary Examiner Adam D Houston (57) ABSTRACT A type I phase locked loop
(PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured …
(PLL) includes an oscillator and a feedback path to a phase detector. The PLL is configured …
Fractional divider with phase shifter and fractional phase locked loop including the same
LIM Baekmin, S Kim, S Oh - US Patent 11,777,510, 2023 - Google Patents
A fractional divider processing circuitry is to receive one of a plurality of clock signals as an
input clock signal, and generate a first division clock signal based on the input clock signal …
input clock signal, and generate a first division clock signal based on the input clock signal …
DTC nonlinearity correction
H Zhang, A Jain, Y Chen, RS Casey, W Lin… - US Patent …, 2024 - Google Patents
Embodiments herein describe correcting nonlinearity in a Digital-to-Time Converter (DTC)
by relaxing a DTC linearity requirement, which results in the correction being co-adapted …
by relaxing a DTC linearity requirement, which results in the correction being co-adapted …
Apparatus and methods for improved transmit power
YH Chang, PC Huang, PA Wu, WH Chiu… - US Patent …, 2023 - Google Patents
US11601156B2 - Apparatus and methods for improved transmit power - Google Patents
US11601156B2 - Apparatus and methods for improved transmit power - Google Patents …
US11601156B2 - Apparatus and methods for improved transmit power - Google Patents …