COAXIAL: A CXL-Centric Memory System for Scalable Servers

A Cho, A Saxena, M Qureshi… - … Conference for High …, 2024 - ieeexplore.ieee.org
The memory system is a major performance determinant for server processors. Ever-
growing core counts and datasets demand higher memory bandwidth and capacity. DDR …

A case for cxl-centric server processors

A Cho, A Saxena, M Qureshi, A Daglis - arXiv preprint arXiv:2305.05033, 2023 - arxiv.org
The memory system is a major performance determinant for server processors. Ever-
growing core counts and datasets demand higher bandwidth and capacity as well as lower …

Fat caches for scale-out servers

S Volos, D Jevdjic, B Falsafi, B Grot - Ieee Micro, 2017 - ieeexplore.ieee.org
Emerging scale-out servers are characterized by massive memory footprints and bandwidth
requirements. On-chip stacked DRAM caches have been proposed to provide the required …

Analytical modeling and performance benchmarking of on-chip interconnects with rough surfaces

S Kumar, R Sharma - IEEE Transactions on Multi-Scale …, 2017 - ieeexplore.ieee.org
In planar on-chip copper interconnects, conductor losses due to surface roughness
demands explicit consideration for accurate modeling of their performance metrics. This is …

AstriFlash A Flash-Based System for Online Services

S Gupta, Y Oh, L Yan, M Sutherland… - … Symposium on High …, 2023 - ieeexplore.ieee.org
Modern datacenters host datasets in DRAM to offer large-scale online services with tight tail-
latency requirements. Unfortunately, as DRAM is expensive and increasingly difficult to …

Design of energy-aware interconnects for next generation micro systems

R Sharma, S Kumar - CSI Transactions on ICT, 2019 - Springer
This paper presents an overview of the problem of surface roughness in ultra-scaled Copper
(Cu) interconnects. It is seen that surface roughness can severely degrade the electrical and …