The growing complexity of multi-core architectures has motivated a wide range of software
mechanisms to improve the orchestration of parallel executions. Task parallelism has …

Redundant computations appear during the execution of real programs. Multiple factors
contribute to these unnecessary computations, such as repetitive inputs and patterns, calling …

Stacked DRAM memories have become a reality in High-Performance Computing (HPC)
architectures. These memories provide much higher bandwidth while consuming less power …

In high performance processors, the design of on-chip memory hierarchies is crucial for
performance and energy efficiency. Current processors rely on large shared Non-Uniform …

Last-level caches (LLCs) bridge the processor/memory speed gap and reduce energy
consumed per access. Unfortunately, LLCs are poorly utilized because of the relatively large …

Embedded systems are presented today with the challenge of a very rapidly evolving
application diversity followed by increased programming and computational complexity …

With increasing core counts, the scalability of directory-based cache coherence has become
a challenging problem. To reduce the area and power needs of the directory, recent …

Embedded multi-core systems are increasingly in use. As established single-core design
methodologies are often not applicable out of the box, novel design-time optimization …

The memory topology of high-performance computing platforms is becoming more complex.
Future exascale platforms in particular are expected to feature multiple types of memory …

In this paper, we examine the relation between onomatopoeia and images using a large
number of Web images. The objective of this paper is to examine if the images …