Challenges and limitations of CMOS scaling for FinFET and beyond architectures
A Razavieh, P Zeitzoff, EJ Nowak - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
Scaling trends of FinFET architecture, with focus on Front-End-of-Line (FEOL), and Middle-of-
Line (MOL) device parameters, is systematically investigated. It is concluded that the …
Line (MOL) device parameters, is systematically investigated. It is concluded that the …
Demonstration of a nanosheet FET with high thermal conductivity material as buried oxide: Mitigation of self-heating effect
Self-heating-induced thermal degradation is a severe issue in nonplanar MOS architectures.
Especially in stacked gate-all-around (GAA) nanosheet FET (NSFET), the self-heating effect …
Especially in stacked gate-all-around (GAA) nanosheet FET (NSFET), the self-heating effect …
Titanium-based ohmic contacts in advanced CMOS technology
S Mao, J Luo - Journal of Physics D: Applied Physics, 2019 - iopscience.iop.org
Since the contact resistance characterized by a specific contact resistivity (ρ c) in the
source/drain (S/D) regions is becoming a bottleneck for further improving device …
source/drain (S/D) regions is becoming a bottleneck for further improving device …
Modeling, Simulation and Analysis of Surface Potential and Threshold Voltage: Application to High-K Material HfO2 Based FinFET
In this study, an analytical model for surface potential and threshold voltage for undoped (or
lightly) doped tri-gate Fin Field Effect Transistor (TG-FinFET) is proposed and validated …
lightly) doped tri-gate Fin Field Effect Transistor (TG-FinFET) is proposed and validated …
A snapshot review on metal–semiconductor contact exploration for 7-nm CMOS technology and beyond
H Yu, M Schaekers, JL Everaert, N Horiguchi… - MRS Advances, 2022 - Springer
Contact resistances take a significant portion of on-state resistances of advanced Si CMOS
transistors. As a result, a metal–semiconductor contact resistivity (ρ c) of sub-10–8 Ω cm2 or …
transistors. As a result, a metal–semiconductor contact resistivity (ρ c) of sub-10–8 Ω cm2 or …
A refined ladder transmission line model for the extraction of significantly low specific contact resistivity
In this article, a refined ladder transmission line model (R-LTLM) test structure capable of
extracting significantly low specific contact resistivity () eliminating parasitic metal resistance …
extracting significantly low specific contact resistivity () eliminating parasitic metal resistance …
High-Performance Ge PIN Photodiodes on a 200 mm Insulator with a Resonant Cavity Structure and Monolayer Graphene Absorber for SWIR Detection
J Yu, X Zhao, Y Miao, J Su, Z Kong, H Li… - ACS Applied Nano …, 2024 - ACS Publications
High-responsivity and low dark current resonant-cavity-enhanced (RCE) Ge PIN
photodiodes with a monolayer graphene absorber were demonstrated on a 200 mm …
photodiodes with a monolayer graphene absorber were demonstrated on a 200 mm …
Next Generation Gate-all-around Device Design for Continued Scaling Beyond 2 nm Logic
We explore GAA transistor design elements for performance scaling beyond 2nm
technology node. We examine the various resistance components of a 1 st generation GAA …
technology node. We examine the various resistance components of a 1 st generation GAA …
A comprehensive study of device variability of sub-5 nm nanosheet transistors and interplay with quantum confinement variation
H Luo, R Li, X Miao, X Wang - Science China Information Sciences, 2023 - Springer
Conclusion The comprehensive studies aimed at the interplay between the quantum
confinement effect and device statistical variability among process design of experiments for …
confinement effect and device statistical variability among process design of experiments for …
Vertically stacked cantilever n-type poly-Si junctionless nanowire transistor and its series resistance limit
CCC Chung, CH Shen, JY Lin… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
We had successfully suspended the vertically stacked cantilever (VSC) nanowire by two
approaches: 1) inserting a SiN layer as reinforcement to sustain the gate-stack thermal …
approaches: 1) inserting a SiN layer as reinforcement to sustain the gate-stack thermal …