In-memory database acceleration on FPGAs: a survey

J Fang, YTB Mulder, J Hidders, J Lee, HP Hofstee - The VLDB Journal, 2020 - Springer
While FPGAs have seen prior use in database systems, in recent years interest in using
FPGA to accelerate databases has declined in both industry and academia for the following …

Co-design hardware and algorithm for vector search

W Jiang, S Li, Y Zhu, J de Fine Licht, Z He… - Proceedings of the …, 2023 - dl.acm.org
Vector search has emerged as the foundation for large-scale information retrieval and
machine learning systems, with search engines like Google and Bing processing tens of …

Efficient spmv operation for large and highly sparse matrices using scalable multi-way merge parallelization

F Sadi, J Sweeney, TM Low, JC Hoe, L Pileggi… - Proceedings of the …, 2019 - dl.acm.org
The importance of Sparse Matrix dense Vector multiplication (SpMV) operation in graph
analytics and numerous scientific applications has led to development of custom …

Reconfigurable hardware accelerators: Opportunities, trends, and challenges

C Wang, W Lou, L Gong, L Jin, L Tan, Y Hu, X Li… - arXiv preprint arXiv …, 2017 - arxiv.org
With the emerging big data applications of Machine Learning, Speech Recognition, Artificial
Intelligence, and DNA Sequencing in recent years, computer architecture research …

{FAERY}: An {FPGA-accelerated} embedding-based retrieval system

C Zeng, L Luo, Q Ning, Y Han, Y Jiang, D Tang… - … USENIX Symposium on …, 2022 - usenix.org
Embedding-based retrieval (EBR) is widely used in recommendation systems to retrieve
thousands of relevant candidates from a large corpus with millions or more items. A good …

FANS: FPGA-accelerated near-storage sorting

W Qiao, J Oh, L Guo, MCF Chang… - 2021 IEEE 29th Annual …, 2021 - ieeexplore.ieee.org
Large-scale sorting is always an important yet demanding task for data center applications.
In addition to powerful processing capability, high-performance sorting system requires …

High-performance hardware merge sorter

S Mashimo, T Van Chu, K Kise - 2017 IEEE 25th Annual …, 2017 - ieeexplore.ieee.org
State-of-the-art studies show that FPGA-based hardware merge sorters (HMSs) can achieve
superior performance compared with optimized algorithms on CPUs and GPUs. The …

TopSort: A high-performance two-phase sorting accelerator optimized on HBM-based FPGAs

W Qiao, L Guo, Z Fang, MCF Chang… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
The emergence of high-bandwidth memory (HBM) brings new opportunities to boost the
performance of sorting acceleration on FPGAs, which was conventionally bounded by the …

High-Throughput Split-Tree Architecture for Nonbinary SCL Polar Decoder

Y Tao, C Choi - 2022 IEEE International Symposium on Circuits …, 2022 - ieeexplore.ieee.org
Nonbinary polar codes defined over Galois field GF (q) have shown improved error-
correction performance than binary polar codes using successive-cancellation list (SCL) …

RTHS: A low-cost high-performance real-time hardware sorter, using a multidimensional sorting algorithm

A Norollah, D Derafshi, H Beitollahi… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
This paper proposes a novel hardware-based multidimensional sorting algorithm and its
respective architecture, called real-time hardware sorter (RTHS), for emerging data intensive …