Enhanced IP-XACT platform descriptions for automatic generation from UML/MARTE of fast performance models for DSE
This paper presents a framework which, starting from a UML/MARTE model of the
embedded system, relies on an enhanced IP-XACT description of the platform for the …
embedded system, relies on an enhanced IP-XACT description of the platform for the …
Extending UML for electronic systems design: A code generation perspective
Y Vanderperren, W Mueller, D He, F Mischkalla… - Design Technology for …, 2012 - Springer
Abstract The Unified Modeling Language (UML) is now widely accepted by the software
community. More recently, UML has attracted attention as a unification language for systems …
community. More recently, UML has attracted attention as a unification language for systems …
A Model-Driven Platform for Dynamic Partially Reconfigurable Architectures: A Case Study of a Watermarking System
The reconfigurable feature of FPGAs (Field-Programmable Gate Arrays) has made them a
very attractive solution for implementing adaptive systems-on-chip. However, this implies …
very attractive solution for implementing adaptive systems-on-chip. However, this implies …
A high-level methodology for automatically generating dynamic partially reconfigurable systems using IP-XACT and the UML MARTE profile
Abstract Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a
method to increase the flexibility of FPGA designs. However, using DPR for building …
method to increase the flexibility of FPGA designs. However, using DPR for building …
Combining SystemC, IP-XACT and UML/MARTE in model-based SoC design
JF Le Tallec, J DeAntoni, R De Simone… - Workshop on Model …, 2011 - inria.hal.science
Modern SoC design may rely on models, or on highlevel description languages. Although
very close, the benefits obtained from either sides can be substantially different (and …
very close, the benefits obtained from either sides can be substantially different (and …
[HTML][HTML] Abeto: An automated benchmarking tool to manage heterogeneous IP core databases
Abstract System-level design makes use of building blocks, known as soft IP cores, to build
complex developments. The usage of these IP cores allows to reduce design and …
complex developments. The usage of these IP cores allows to reduce design and …
High-level modelling and automatic generation of dynamicaly reconfigurable systems
G Ochoa, EB Bourennane, H Rabah… - Proceedings of the …, 2011 - ieeexplore.ieee.org
Dynamic Partial Reconfiguration (DPR) has been introduced in recent years as a method to
increase the flexibility of FPGA designs. However, using DPR for building complex systems …
increase the flexibility of FPGA designs. However, using DPR for building complex systems …
An MDE approach for rapid prototyping and implementation of dynamic reconfigurable systems
This article presents a co-design methodology based on RecoMARTE, an extension to the
well-known UML MARTE profile, which is used for the specification and automatic …
well-known UML MARTE profile, which is used for the specification and automatic …
A UML profile for SysML-based comodeling for embedded systems simulation and synthesis
F Mischkalla, W Müller, D He - Proceedings of the M-BED …, 2010 - ris.uni-paderborn.de
It's wide application in the area of software engineering, UML is still not fully accepted for
other engineering domains like for electronic systems design. The main obstacle is due to a …
other engineering domains like for electronic systems design. The main obstacle is due to a …
A framework for the generation from UML/MARTE models of IPXACT HW platform descriptions for multi-level performance estimation
F Herrera, E Villar - FDL 2011 Proceedings, 2011 - ieeexplore.ieee.org
This paper presents a framework which automates the generation of the IP/XACT-based
description of the HW platform of an embedded system from a UML/MARTE model of such a …
description of the HW platform of an embedded system from a UML/MARTE model of such a …