The fabrication of next-generation semiconductor devices has created a need for low-
temperature (≤ 400 C) deposition of highly-conformal (> 95%) SiO 2, SiN x, and SiC films …

Abstract Tri-Gate (TG) FinFETs are the most reliable option to get into deeply scaled gate
lengths. This paper analyses an optimized 5 nm gate length (LG) n-channel TG Junctionless …

Silicon (Si) ultrathin junctionless (JL) n-FinFET with LG= 3 nm and 1 nm are explored for the
first time by invoking Hf x Ti 1-x O 2 based high-k gate dielectric. The 3D device performance …

Reconfigurable logic circuits implemented by two-dimensional (2D) ambipolar
semiconductors provide a prospective solution for the post-Moore era. It is still a challenge …

In this paper, for the first time, we have investigated the DC and analog/RF performance
metrics of 3 nm gate length (LG) silicon-on-insulator (SOI) FinFET using Hf x Ti 1− x O 2 high …

In this paper, we have studied the impact of various dielectric single-k (Sk) and dual-k (Dk)
spacers on optimized Junctionless (JL) FinFET at nano-regime by using hetero-dielectric …

Multi‐fin devices are the most reliable option for terahertz (THz) frequency applications at
nano‐regime. In this work impact of spacer engineering on multi‐fin SOI FET performance is …

Through a comparative analysis of gate-all-around field-effect transistors (GAAFETs) with
the same layout footprint as FinFETs of 3-nm technology nodes, the effect of the tapered fin …

The spacer design of the negative-capacitance FinFET (NC-FinFET) is investigated by using
Sentaurus technology computer-aided design (TCAD). The spacer affects not only the gate …

Parasitic capacitance in nanoscale FETs is becoming a dominant component of the total
device capacitance which degrades device and circuit performance. This problem is …