[图书][B] Analog-to-digital conversion
MJM Pelgrom, MJM Pelgrom - 2013 - Springer
Several classifications exist of Nyquist-rate analog-to-digital converters. In this chapter the
converters are subdivided in parallel search, sequential search, and linear search. Each of …
converters are subdivided in parallel search, sequential search, and linear search. Each of …
A 12 bit 2.9 GS/s DAC With IM3 60 dBc Beyond 1 GHz in 65 nm CMOS
CH Lin, FML Van Der Goes, JR Westra… - IEEE Journal of Solid …, 2009 - ieeexplore.ieee.org
A 12 bit 2.9 GS/s current-steering DAC implemented in 65 nm CMOS is presented, with an
IM3≪-60~dBc beyond 1 GHz while driving a 50 Ω load with an output swing of 2.5 V_\rmppd …
IM3≪-60~dBc beyond 1 GHz while driving a 50 Ω load with an output swing of 2.5 V_\rmppd …
A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With 70 dB SFDR up to 500 MHz
WH Tseng, CW Fan, JT Wu - IEEE Journal of Solid-State …, 2011 - ieeexplore.ieee.org
A current-steering digital-to-analog converter (DAC) was fabricated using a 90 nm CMOS
technology. Its dynamic performance is enhanced by adopting a digital random return-to …
technology. Its dynamic performance is enhanced by adopting a digital random return-to …
A 14 bit 200 MS/s DAC with SFDR> 78 dBc, IM3<-83 dBc and NSD<-163 dBm/Hz across the whole nyquist band enabled by dynamic-mismatch mapping
Y Tang, J Briaire, K Doris… - IEEE Journal of Solid …, 2011 - ieeexplore.ieee.org
This paper presents a 14 bit 200 MS/s current-steering DAC with a novel digital calibration
technique called dynamic-mismatch mapping (DMM). By optimizing the switching sequence …
technique called dynamic-mismatch mapping (DMM). By optimizing the switching sequence …
[图书][B] Advanced data converters
G Manganaro - 2011 - books.google.com
Need to get up to speed quickly on the latest advances in high performance data
converters? Want help choosing the best architecture for your application? With everything …
converters? Want help choosing the best architecture for your application? With everything …
A heterogeneous 3D-IC consisting of two 28 nm FPGA die and 32 reconfigurable high-performance data converters
C Erdmann, D Lowney, A Lynam… - IEEE Journal of Solid …, 2014 - ieeexplore.ieee.org
A reconfigurable heterogeneous 3D-IC is assembled from two 28 nm FPGA die with 580 k
logic cells and two 65 nm mixed signal die on a 65 nm interposer in a 35 mm 2 CS-BGA …
logic cells and two 65 nm mixed signal die on a 65 nm interposer in a 35 mm 2 CS-BGA …
A 10–Bit 1.6-GS/s 27-mW current-steering D/A converter with 550-MHz 54-dB SFDR bandwidth in 130-nm CMOS
P Palmers, MSJ Steyaert - … on Circuits and Systems I: Regular …, 2010 - ieeexplore.ieee.org
This paper presents a 10-bit 5-5 segmented current-steering digital-to-analog converter
implemented in a standard 130-nm CMOS technology. It achieves full-Nyquist performance …
implemented in a standard 130-nm CMOS technology. It achieves full-Nyquist performance …
Dynamic element matching to prevent nonlinear distortion from pulse-shape mismatches in high-resolution DACs
KL Chan, J Zhu, I Galton - IEEE Journal of Solid-State Circuits, 2008 - ieeexplore.ieee.org
This paper shows analytically and experimentally that properly-designed dynamic element
matching (DEM) eliminates pulse shape, timing, and amplitude errors arising from …
matching (DEM) eliminates pulse shape, timing, and amplitude errors arising from …
A 130 nm CMOS 6-bit full Nyquist 3 GS/s DAC
X Wu, P Palmers, MSJ Steyaert - IEEE journal of solid-state …, 2008 - ieeexplore.ieee.org
This paper presents a 6-bit very high-speed, low-power digital-to-analog converter (DAC). It
is based on a current steering binary weighted architecture and achieves 10-bit static …
is based on a current steering binary weighted architecture and achieves 10-bit static …
A 12-bit 2 GS/s dual-rate hybrid DAC with pulse-error pre-distortion and in-band noise cancellation achieving> 74 dBc SFDR and<− 80 dBc IM3 up to 1 GHz in 65 nm …
S Su, MSW Chen - IEEE Journal of Solid-State Circuits, 2016 - ieeexplore.ieee.org
This paper presents a 12-bit 2 GS/s dual-rate hybrid DAC using bandwidth-and linearity-
enhancement techniques. The proposed pulsed-error pre-distortion scheme enhances DAC …
enhancement techniques. The proposed pulsed-error pre-distortion scheme enhances DAC …