Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

O Marinov, MJ Deen, JA Jiménez-Tejada - Physics Reports, 2022 - Elsevier
By the continuing downscaling of sub-micron transistors in the range of few to sub-
decananometers, we focus on the increasing relative level of the low-frequency noise in …

Prerequisite-driven deep knowledge tracing

P Chen, Y Lu, VW Zheng, Y Pian - 2018 IEEE international …, 2018 - ieeexplore.ieee.org
Knowledge tracing serves as the key technique in the computer supported education
environment (eg, intelligent tutoring systems) to model student's knowledge states. While the …

Multirate timestamp modeling for ultralow-jitter frequency synthesis: A tutorial

Y Hu, T Siriburanon… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
In this tutorial brief, we introduce a unified wideband phase-noise theory framework of
frequency synthesis based on a multirate timestamp modeling with “two-variables”. We …

A charge-sharing locking technique with a general phase noise theory of injection locking

Y Hu, X Chen, T Siriburanon, J Du… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
This article presents a millimeter-wave (mmW) frequency synthesizer based on a new
charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge …

Analysis of VCO phase noise in charge-pump phase-locked loops

P Maffezzoni, S Levantino - … on Circuits and Systems I: Regular …, 2012 - ieeexplore.ieee.org
This paper presents a phase noise analysis of charge-pump phase-locked-loops.
Fundamental results from the theory of discrete-time systems are employed to derive closed …

A dividerless PLL with low power and low reference spur by aperture-phase detector and phase-to-analog converter

D Cai, H Fu, J Ren, W Li, N Li, H Yu… - IEEE Transactions on …, 2012 - ieeexplore.ieee.org
A 2.1-GHz dividerless PLL with low power, low reference spur and low in-band phase noise
is introduced in this paper. A new phase detection mechanism using aperture-phase …

Efficient behavioral simulation of charge-pump phase-locked loops

M Leoncini, A Bonfanti, S Levantino… - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
The simulation of the full netlist of a phase locked loop (PLL) is resource demanding due to
the prohibitive time needed to derive output noise, spurs, and transient performance from …

Linear time-variant modeling and analysis of all-digital phase-locked loops

IL Syllaios, PT Balsara - … Transactions on Circuits and Systems I …, 2012 - ieeexplore.ieee.org
All-digital phase-locked loops (ADPLL) are inherently multirate systems with time-varying
behavior. In support of this statement linear time-variant (LTV) models of ADPLL are …

Derivation of a small-signal harmonic model for closed-loop power converters based on the state-variable sensitivity method

KL Lian - IEEE Transactions on Circuits and Systems I: Regular …, 2011 - ieeexplore.ieee.org
<? Pub Dtl=""?> An admittance or impedance matrix of a power converter is highly desirable
for harmonic analysis of a power system. However, power converters are inherently …

[图书][B] Mixed-signal circuit design driven by analysis: ADCs, comparators, and PLLs

H Xu - 2018 - search.proquest.com
Mixed signal circuit design often involves circuits that are time-varying or highly non-linear,
which further results in systems that are difficult to characterize using established …