Heteroflow: An accelerator programming model with decoupled data placement for software-defined fpgas
To achieve high performance with FPGA-equipped heterogeneous compute systems, it is
crucial to co-optimize data placement and compute scheduling to maximize data reuse and …
crucial to co-optimize data placement and compute scheduling to maximize data reuse and …
Fluid: An asynchronous high-level synthesis tool for complex program structures
Current high-level synthesis (HLS) tools that generate synchronous logic construct a state
machine that schedules program operations in each clock cycle. Rather than this centralized …
machine that schedules program operations in each clock cycle. Rather than this centralized …
FADO: F loorplan-A ware D irective O ptimization for High-Level Synthesis Designs on Multi-Die FPGAs
Multi-die FPGAs are widely adopted to deploy large-scale hardware accelerators. Two
factors impede the performance optimization of high-level synthesis (HLS) designs …
factors impede the performance optimization of high-level synthesis (HLS) designs …
Hl-pow: learning-assisted pre-RTL power modeling and optimization for FPGA HLS
High-level synthesis (HLS) enables designers to customize hardware designs without the
need for delving into low-level hardware details. However, it is still challenging to establish …
need for delving into low-level hardware details. However, it is still challenging to establish …
FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs
Multi-die FPGAs are widely adopted for large-scale accelerators, but optimizing high-level
synthesis designs on these FPGAs faces two challenges. First, the delay caused by die …
synthesis designs on these FPGAs faces two challenges. First, the delay caused by die …
Scheduling information-guided efficient high-level synthesis design space exploration
X Qian, J Shi, L Shi, H Zhang, L Bian… - 2022 IEEE 40th …, 2022 - ieeexplore.ieee.org
High-level synthesis (HLS) transforms designs specified by high-level programming
language into RTL designs. In order to get the optimal designs, many design space …
language into RTL designs. In order to get the optimal designs, many design space …
Syncopation: Adaptive Clock Management for High-Level Synthesis Generated Circuits on FPGAs
High-level synthesis (HLS) tools improve hardware designer productivity by enabling
software design techniques during hardware development. During HLS the delay of paths …
software design techniques during hardware development. During HLS the delay of paths …
A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs
G Brignone, MT Lazarescu… - 2023 IEEE 41st …, 2023 - ieeexplore.ieee.org
High-level synthesis (HLS) enhances digital hardware design productivity through a high
abstraction level. Even if the HLS abstraction prevents fine-grained manual register-transfer …
abstraction level. Even if the HLS abstraction prevents fine-grained manual register-transfer …
Using Multiple Clocks in Highlevel Synthesis to overcome unbalanced clock cycles
YB Asher, I Qashqoush - … Multicore/Many-core Systems-on-Chip …, 2023 - ieeexplore.ieee.org
High-level Synthesis (HLS) is a technique to compile C/C++ algorithmic code directly to
hardware circuits (Verilog/VHDL). Typically, HLS schedulers partition the graph of …
hardware circuits (Verilog/VHDL). Typically, HLS schedulers partition the graph of …
Adaptive Clock Management of HLS-generated Circuits on FPGAs
In this article, we present Syncopation, a performance-boosting fine-grained timing analysis
and adaptive clock management technique for High-Level Synthesis-generated circuits …
and adaptive clock management technique for High-Level Synthesis-generated circuits …