3D-MAPS: 3D massively parallel processor with stacked memory
SK Lim, SK Lim - Design for High Performance, Low Power, and …, 2013 - Springer
This chapter describes the architecture, design, analysis, and simulation and measurement
results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built …
results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built …
Fabrication cost analysis and cost-aware design space exploration for 3-D ICs
3-D integration technology is emerging as an attractive alternative to increase the transistor
count for future chips. The majority of the existing 3-D integrated circuit (IC) research is …
count for future chips. The majority of the existing 3-D integrated circuit (IC) research is …
Design and analysis of 3D-MAPS (3D massively parallel processor with stacked memory)
This paper describes the architecture, design, analysis, and simulation and measurement
results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built …
results of the 3D-MAPS (3D massively parallel processor with stacked memory) chip built …
Design of cross-point metal-oxide ReRAM emphasizing reliability and cost
Metal-Oxide Resistive Random Access Memory (ReRAM) technology is gaining popularity
due to its superior write bandwidth, high density, and low operating power. An ReRAM array …
due to its superior write bandwidth, high density, and low operating power. An ReRAM array …
Memory and storage system design with nonvolatile memory technologies
The memory and storage system, including processor caches, main memory, and storage, is
an important component of various computer systems. The memory hierarchy is becoming a …
an important component of various computer systems. The memory hierarchy is becoming a …
Cost-aware exploration for chiplet-based architecture with advanced packaging technologies
The chiplet-based System-in-Package~(SiP) technology enables more design flexibility via
various inter-chiplet connection and heterogeneous integration. However, it is not known …
various inter-chiplet connection and heterogeneous integration. However, it is not known …
Parana: A parallel neural architecture considering thermal problem of 3d stacked memory
Recent advances in deep learning (DL) have stimulated increasing interests in neural
networks (NN). From the perspective of operation type and network architecture, deep …
networks (NN). From the perspective of operation type and network architecture, deep …
Economizing TSV resources in 3-D network-on-chip design
The confluence of 3-D integration and network-on-chip (NoC) provides an effective solution
to the scalability problem of on-chip interconnects. In 3-D integration, through-silicon via …
to the scalability problem of on-chip interconnects. In 3-D integration, through-silicon via …
Overview of 3-D architecture design opportunities and techniques
Three-dimensional (3-D) integration, a breakthrough technology to achieve “More Moore
and More Than Moore,” provides numerous benefits, eg, higher performance, lower power …
and More Than Moore,” provides numerous benefits, eg, higher performance, lower power …
Parka: Thermally insulated nanophotonic interconnects
Y Demir, N Hardavellas - … of the 9th International Symposium on …, 2015 - dl.acm.org
Silicon-photonics are emerging as the prime candidate technology for energy-efficient on-
chip interconnects at future process nodes. However, current designs are primarily based on …
chip interconnects at future process nodes. However, current designs are primarily based on …