Since the seventies, positron emission tomography (PET) has become an invaluable
medical molecular imaging modality with an unprecedented sensitivity at the picomolar …

This article introduces a low-jitter low-spur fractional-N phase-locked loop (PLL) adopting a
new concept of a time-mode arithmetic unit (TAU) for phase error extraction. The TAU is a …

This paper presents the first fully integrated radiation-tolerant All-Digital Phase-Locked Loop
(PLL) and Clock and Data Recovery (CDR) circuit for wireline communication applications …

Digital integrated circuits have significantly benefited from technology scaling down, while
conventional analog integrated circuits suffer from more design constraints. In recent years …

This article presents a power-efficient low-jitter fractional-N digital phase-locked loop (DPLL)
that resolves phase error (PE) in the fully differential voltage (FDV) domain. Compared with …

In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture
based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra …

In this brief, we introduce a 3.2-4 GHz three-winding transformer-based class-F digitally
controlled oscillator (DCO) with a DC-DC booster for energy harvesting applications. A π …

Digital-to-time converter (DTC) based quantization noise cancellation (QNC) has recently
been shown to enable excellent fractional-PLL performance, but it requires a highly-linear …

A phase-coherent technique for multiple all-digital phase-locked loops (ADPLLs) is
presented and developed in this paper to target a 57-63-GHz multiple-input multiple-output …

Design of a CMOS compact tunable differential active inductor (DAI) suitable to low-cost and
multi-standard systems is presented. The structure uses only active components, based on …