Temperature sensitivity analysis of inner-gate engineered JL-SiNT-FET: An Analog/RF prospective
This paper explores the temperature sensitivity of Inner-gate engineered junctionless silicon
nanotube FET (JL-SiNT-FET) on analog/RF performance. It is found that the reduction in the …
nanotube FET (JL-SiNT-FET) on analog/RF performance. It is found that the reduction in the …
Study of 6T SRAM cell using high-k gate dielectric based junctionless silicon nanotube FET
This paper investigates the performance of 6 T SRAM cell using high-K gate dielectric based
junctionless silicon nanotube FET (JLSiNTFET). It is observed that the use of high-K gate …
junctionless silicon nanotube FET (JLSiNTFET). It is observed that the use of high-K gate …
Study of temperature effect on junctionless Si nanotube FET concerning analog/RF performance
This paper for the first time investigates the effect of temperature variation on analog/RF
performance of SiO 2 as well as high-K gate dielectric based junctionless silicon nanotube …
performance of SiO 2 as well as high-K gate dielectric based junctionless silicon nanotube …
Performance analysis of junctionless DG‐MOSFET‐based 6T‐SRAM with gate‐stack configuration
In this work, the investigation of high‐K gate‐stack‐based junctionless (JL) double‐gate
(DG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is carried out to study the …
(DG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is carried out to study the …
Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM
This work investigates the delay performance of junctionless silicon nanotube (JLSiNT) field‐
effect transistor (FET) based 6T SRAM cell. The study demonstrates that the delay …
effect transistor (FET) based 6T SRAM cell. The study demonstrates that the delay …
Channel thickness dependency of high-k gate dielectric based double-gate CMOS inverter
S Tayal, P Samrat, V Keerthi… - … Journal of Nano …, 2020 - search.proquest.com
This work investigates the channel thickness dependency of high-k gate dielectric-based
complementary metal-oxide-semiconductor (CMOS) inverter circuit built using a …
complementary metal-oxide-semiconductor (CMOS) inverter circuit built using a …
Performance investigation of different low power SRAM cell topologies using stacked-channel tri-gate junctionless FinFET
At the sub-22 nm technology node, junctionless FinFETs are regarded as advantageous
alternatives for conventional FinFET due to their simpler fabrication and uniform doping …
alternatives for conventional FinFET due to their simpler fabrication and uniform doping …
Performance investigation of stacked-channel junctionless Tri-Gate FinFET 8T-SRAM cell
Junctionless FinFET devices are a substitute for conventional FinFET devices due to their
short channel effects and easy manufacturing at sub 22 nm technology node. The …
short channel effects and easy manufacturing at sub 22 nm technology node. The …
Impact of ion implantation on stacked oxide cylindrical gate junctionless accumulation mode MOSFET: An electrical and circuit level analysis
This article analyses the effect of ion implantation on electrical and circuit-level
characteristics of stacked oxide cylindrical gate (CG) junctionless accumulation mode (JAM) …
characteristics of stacked oxide cylindrical gate (CG) junctionless accumulation mode (JAM) …
A 2-bit Multiplication Operation using Si-SiGe-Si Channel FinFET 8T-SRAM Cell
The Compute-in-memory (CIM) architecture has been offered as an emerging solution to the
Von-Neumann computing architecture's memory wall. The CIM design embeds functionality …
Von-Neumann computing architecture's memory wall. The CIM design embeds functionality …