Temperature sensitivity analysis of inner-gate engineered JL-SiNT-FET: An Analog/RF prospective

S Tayal, V Mittal, S Jadav, S Gupta, A Nandi, B Krishan - Cryogenics, 2020 - Elsevier
This paper explores the temperature sensitivity of Inner-gate engineered junctionless silicon
nanotube FET (JL-SiNT-FET) on analog/RF performance. It is found that the reduction in the …

Study of 6T SRAM cell using high-k gate dielectric based junctionless silicon nanotube FET

S Tayal, A Nandi - Superlattices and Microstructures, 2017 - Elsevier
This paper investigates the performance of 6 T SRAM cell using high-K gate dielectric based
junctionless silicon nanotube FET (JLSiNTFET). It is observed that the use of high-K gate …

Study of temperature effect on junctionless Si nanotube FET concerning analog/RF performance

S Tayal, A Nandi - Cryogenics, 2018 - Elsevier
This paper for the first time investigates the effect of temperature variation on analog/RF
performance of SiO 2 as well as high-K gate dielectric based junctionless silicon nanotube …

Performance analysis of junctionless DG‐MOSFET‐based 6T‐SRAM with gate‐stack configuration

S Tayal, A Nandi - Micro & Nano Letters, 2018 - Wiley Online Library
In this work, the investigation of high‐K gate‐stack‐based junctionless (JL) double‐gate
(DG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is carried out to study the …

Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM

S Tayal, A Nandi - Micro & Nano Letters, 2018 - Wiley Online Library
This work investigates the delay performance of junctionless silicon nanotube (JLSiNT) field‐
effect transistor (FET) based 6T SRAM cell. The study demonstrates that the delay …

Channel thickness dependency of high-k gate dielectric based double-gate CMOS inverter

S Tayal, P Samrat, V Keerthi… - … Journal of Nano …, 2020 - search.proquest.com
This work investigates the channel thickness dependency of high-k gate dielectric-based
complementary metal-oxide-semiconductor (CMOS) inverter circuit built using a …

Performance investigation of different low power SRAM cell topologies using stacked-channel tri-gate junctionless FinFET

D Singh, S Chaudhary, B Dewan, M Yadav - Microelectronics Journal, 2024 - Elsevier
At the sub-22 nm technology node, junctionless FinFETs are regarded as advantageous
alternatives for conventional FinFET due to their simpler fabrication and uniform doping …

Performance investigation of stacked-channel junctionless Tri-Gate FinFET 8T-SRAM cell

D Singh, S Chaudhary, B Dewan… - Engineering Research …, 2024 - iopscience.iop.org
Junctionless FinFET devices are a substitute for conventional FinFET devices due to their
short channel effects and easy manufacturing at sub 22 nm technology node. The …

Impact of ion implantation on stacked oxide cylindrical gate junctionless accumulation mode MOSFET: An electrical and circuit level analysis

K Baral, PK Singh, G Kumar, AK Singh… - Materials Science in …, 2021 - Elsevier
This article analyses the effect of ion implantation on electrical and circuit-level
characteristics of stacked oxide cylindrical gate (CG) junctionless accumulation mode (JAM) …

A 2-bit Multiplication Operation using Si-SiGe-Si Channel FinFET 8T-SRAM Cell

D Singh, P Yadav, M Yadav - 2023 IEEE International …, 2023 - ieeexplore.ieee.org
The Compute-in-memory (CIM) architecture has been offered as an emerging solution to the
Von-Neumann computing architecture's memory wall. The CIM design embeds functionality …