The breakdown of Dennard scaling has resulted in a decade-long stall of the maximum
operating clock frequencies of processors. To mitigate this issue, computing shifted to multi …

As configurable processing advances, elements from the traditional approaches of both
hardware and software development can be combined by incorporating customized …

This paper presents a novel approach to accelerate program execution by mapping
repetitive traces of executed instructions, called Megablocks, to a runtime reconfigurable …

The acceleration of applications, running on a general purpose processor (GPP), by
mapping parts of their execution to reconfigurable hardware is an approach which does not …

The ability to map instructions running in a microprocessor to a reconfigurable processing
unit (RPU), acting as a coprocessor, enables the runtime acceleration of applications and …

This paper presents an offline tool-chain which automatically extracts loops (Mega blocks)
from Micro Blaze instruction traces and creates a tailored Reconfigurable Processing Unit …

Encapsulating critical computation subgraphs as application-specific instruction set
extensions is an effective technique to enhance the performance and energy efficiency of …

Review Questions............................. 63Bibliography................................ 63Embedded system
development seeks ever more efficient processors and new automation methodologies to …

In this paper, we propose a parallel systematic resampling (PSR) algorithm for particle filters,
which is a new form of systematic resampling (SR). The PSR algorithm makes iterations …

This article presents a reconfigurable hardware/software architecture for binary acceleration
of embedded applications. A Reconfigurable Processing Unit (RPU) is used as a …