US9762250B2 - Cancellation of spurious tones within a phase-locked loop with a time-to-digital
converter - Google Patents US9762250B2 - Cancellation of spurious tones within a phase-locked …

A fractional-N phase-locked loop (PLL) includes a nonlinear time to digital converter that
generates a digital representation of a phase error corresponding to a time difference …

In an embodiment, an integrated circuit may include one or more CPUs, a memory
controller, and a circuit configured to remain powered on when the rest of the SOC is …

Quantization noise in a fractional-N phase-locked loop (PLL) is canceled using a capacitor-
based digital to analog converter (DAC). A phase error is detected between a reference …

(57) ABSTRACT A phase-locked loop (PLL) includes a time to Voltage con Verter to convert
a phase error between a reference signal and a feedback signal of the PLL to one or more …

A controller device can control the time of a slave sub-system in a chain in a base station
system. The controller device comprises a slave transceiver for receiving/transmitting from/to …

A phase-locked loop digital bandwidth calibrator includes a digital loop filter having a gain
multiplier memory and a perturbation unit configured to generate a calibration offset signal to …

BACKGROUND Technical Field Embodiments disclosed herein are related to the field of
mobile devices and, more particularly, to voice/audio control of mobile devices. Description …

Hybrid phase lock loop (PLL) devices are provided that combine advantages of the digital
controlled loop and the analog controlled loop. For example, a hybrid PLL includes a digital …

US9461657B2 - Foreground and background bandwidth calibration techniques for phase-locked
loops - Google Patents US9461657B2 - Foreground and background bandwidth calibration …