Large circuit models: opportunities and challenges
Within the electronic design automation (EDA) domain, artificial intelligence (AI)-driven
solutions have emerged as formidable tools, yet they typically augment rather than redefine …
solutions have emerged as formidable tools, yet they typically augment rather than redefine …
Accurate timing prediction at placement stage with look-ahead rc network
X He, Z Fu, Y Wang, C Liu, Y Guo - Proceedings of the 59th ACM/IEEE …, 2022 - dl.acm.org
Timing closure is a critical but effort-taking task in VLSI designs. In placement stage, a fast
and accurate net delay estimator is highly desirable to guide the timing optimization prior to …
and accurate net delay estimator is highly desirable to guide the timing optimization prior to …
Machine learning for agile fpga design
Field-programmable gate arrays (FPGAs) have become popular means of hardware
acceleration since they offer massive parallelism, flexible configurability, and potentially …
acceleration since they offer massive parallelism, flexible configurability, and potentially …
FlowTune: End-to-end automatic logic optimization exploration via domain-specific multiarmed bandit
Design flows are the explicit combinations of design transformations, primarily involved in
synthesis, placement, and routing processes, to accomplish the design of integrated circuits …
synthesis, placement, and routing processes, to accomplish the design of integrated circuits …
The dawn of ai-native eda: Promises and challenges of large circuit models
Within the Electronic Design Automation (EDA) domain, AI-driven solutions have emerged
as formidable tools, yet they typically augment rather than redefine existing methodologies …
as formidable tools, yet they typically augment rather than redefine existing methodologies …
Transferable pre-synthesis ppa estimation for rtl designs with data augmentation techniques
In modern VLSI design flow, evaluating the quality of register-transfer level (RTL) designs
involves time-consuming logic synthesis using EDA tools, a process that often slows down …
involves time-consuming logic synthesis using EDA tools, a process that often slows down …
SLAP: A supervised learning approach for priority cuts technology mapping
Recently we have seen many works that leverage Machine Learning (ML) techniques in
optimizing Electronic Design Automation (EDA) process. However, the uses of ML …
optimizing Electronic Design Automation (EDA) process. However, the uses of ML …
敏捷设计中基于机器学习的静态时序分析方法综述
贺旭， 王耀， 傅智勇， 李暾， 屈婉霞， 万海… - 计算机辅助设计与图形学 …, 2023 - jcad.cn
随着集成电路规模越来越大, 设计变得越来越复杂. 为了有效地提升设计生产率,
芯片敏捷设计受到越来越广泛的重视. 在芯片RTL-to-GDSII 设计流程中, 敏捷设计方法需要广泛 …
芯片敏捷设计受到越来越广泛的重视. 在芯片RTL-to-GDSII 设计流程中, 敏捷设计方法需要广泛 …
GraPhSyM: Graph Physical Synthesis Model
In this work, we introduce GraPhSyM, a Graph Attention Network (GATv2) model for fast and
accurate estimation of post-physical synthesis circuit delay and area metrics from pre …
accurate estimation of post-physical synthesis circuit delay and area metrics from pre …
MapTune: Advancing ASIC Technology Mapping via Reinforcement Learning Guided Library Tuning
Technology mapping involves mapping logical circuits to a library of cells. Traditionally, the
full technology library is used, leading to a large search space and potential overhead …
full technology library is used, leading to a large search space and potential overhead …