Hardware and software enabled implementation of power profile management instructions in system on chip
R Kaushal, A Gangwar, VM Pusuluri… - US Patent 9,568,970, 2017 - Google Patents
Aspects of the present disclosure relate to a method and system for hybrid and/or distributed
implementation of generation and/or execution of power profile management instructions …
implementation of generation and/or execution of power profile management instructions …
Configurable router for a network on chip (NoC)
J Philip, S Kumar - US Patent 9,742,630, 2017 - Google Patents
Example implementations described herein are directed to a configurable building block,
such as a router, for implementation of a Network on Chip (NoC). The router is …
such as a router, for implementation of a Network on Chip (NoC). The router is …
Systems and methods for facilitating low power on a network-on-chip
JA Bauman, J Rowlands, S Kumar - US Patent 10,452,124, 2019 - Google Patents
Aspects of the present disclosure are directed to a power specification and Network on Chip
(NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC …
(NoC) having a power supervisor (PS) unit. The specification is utilized to generate a NoC …
System and method for visualization of NoC performance based on simulation output
Aspects of the present disclosure are directed to methods, systems, and non-transitory
computer readable mediums for selective visualization and performance characterization of …
computer readable mediums for selective visualization and performance characterization of …
Supporting multicast in NoC interconnect
Example implementations are directed to more efficiently delivering a multicast message to
multiple destination components from a source component. Multicast environment is …
multiple destination components from a source component. Multicast environment is …
System level simulation in Network on Chip architecture
S Kumar, A Patankar, E Norige - US Patent 10,496,770, 2019 - Google Patents
Abstract Systems and methods for performing multi-message transaction based
performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect …
performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect …
System-on-chip (SoC) optimization through transformation and generation of a network-on-chip (NoC) topology
The present disclosure is directed to system-on-chip (SoC) optimization through
transformation and generation of a network-on-chip (NoC) topology. The present disclosure …
transformation and generation of a network-on-chip (NoC) topology. The present disclosure …
QoS in a system with end-to-end flow control and QoS aware buffer allocation
S Kumar - US Patent 9,769,077, 2017 - Google Patents
(Continued) Primary Examiner—Jay P Patel (74) Attorney, Agent, or Firm—Procopio, Cory,
Hargreaves & Savitch LLP (57) ABSTRACT The present disclosure is directed to Quality of …
Hargreaves & Savitch LLP (57) ABSTRACT The present disclosure is directed to Quality of …
Automatic deadlock detection and avoidance in a system interconnect by capturing internal dependencies of IP cores using high level specification
Systems and methods for automatically building a deadlock free inter-communication
network in a multi-core system are described. The example implementations described …
network in a multi-core system are described. The example implementations described …
Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip
J Philip, S Kumar - US Patent 9,825,809, 2017 - Google Patents
Aspects of the present disclosure relates to methods, computer readable mediums, and NoC
architectures/systems/constructions that can automatically mark and configure some …
architectures/systems/constructions that can automatically mark and configure some …