Productisation: A review and research agenda
Productisation relates to the process of analysing a need, defining and combining suitable
elements, tangible and/or intangible, into a product-like defined set of deliverables that is …
elements, tangible and/or intangible, into a product-like defined set of deliverables that is …
State-of-the-art and future directions of high-performance all-digital frequency synthesis in nanometer CMOS
RB Staszewski - IEEE Transactions on Circuits and Systems I …, 2011 - ieeexplore.ieee.org
The past several years have successfully brought all-digital techniques to the RF frequency
synthesis, which could arguably be considered one of the last strong bastions of the …
synthesis, which could arguably be considered one of the last strong bastions of the …
Relay-assisted multiple access with full-duplex multi-packet reception
The effect of full-duplex cooperative relaying in a random access multiuser network is
investigated here. First, we model the self-interference incurred due to full-duplex operation …
investigated here. First, we model the self-interference incurred due to full-duplex operation …
Spur-free multirate all-digital PLL for mobile phones in 65 nm CMOS
RB Staszewski, K Waheed, F Dulger… - IEEE Journal of Solid …, 2011 - ieeexplore.ieee.org
We propose a new multirate architecture of an all-digital PLL (ADPLL) featuring
phase/frequency modulation capability. While the ADPLL approach has already proven its …
phase/frequency modulation capability. While the ADPLL approach has already proven its …
A digital PLL with feedforward multi-tone spur cancellation scheme achieving<–73 dBc fractional spur and<–110 dBc reference spur in 65 nm CMOS
CR Ho, MSW Chen - IEEE Journal of Solid-State Circuits, 2016 - ieeexplore.ieee.org
This paper proposes a fractional-N digital phase-locked loop (DPLL) architecture with
feedforward multi-tone spur cancellation scheme. The proposed cancellation loop is …
feedforward multi-tone spur cancellation scheme. The proposed cancellation loop is …
8-Shaped Inductors: An Essential Addition to RFIC Designers' Toolbox
The rapidly advancing field of millimeter-wave (mm-wave) radio-frequency integrated circuit
(RFIC) design has ushered in an era of remarkable innovation, particularly in the realm of on …
(RFIC) design has ushered in an era of remarkable innovation, particularly in the realm of on …
An all-digital PLL for cellular mobile phones in 28-nm CMOS with− 55 dBc fractional and− 91 dBc reference spurs
We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios,
which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter …
which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter …
Software assisted Digital RF Processor (DRP™) for single-chip GSM radio in 90 nm CMOS
R Staszewski, RB Staszewski, T Jung… - IEEE Journal of Solid …, 2010 - ieeexplore.ieee.org
This paper proposes and describes a new software and application programming interface
view of an RF transceiver. It demonstrates benefits of using highly programmable digital …
view of an RF transceiver. It demonstrates benefits of using highly programmable digital …
A fractional-N DPLL with calibration-free multi-phase injection-locked TDC and adaptive single-tone spur cancellation scheme
CR Ho, MSW Chen - … Transactions on Circuits and Systems I …, 2016 - ieeexplore.ieee.org
This paper proposes a fractional-N digital phase locked loop (DPLL) architecture with
calibration-free multi-phase injection-locked time-to-digital converter (TDC) and gradient …
calibration-free multi-phase injection-locked time-to-digital converter (TDC) and gradient …
A single-pin antenna interface RF front end using a single-MOS DCO-PA and a push–pull LNA
We propose a simple power-efficient sub-1-V fully integrated RF front end (RFE) for 2.4-GHz
transceivers. It introduces the following innovations. First, a function-reuse single-MOS …
transceivers. It introduces the following innovations. First, a function-reuse single-MOS …