Growing core counts have highlighted the need for scalable on-chip coherence
mechanisms. The increase in the number of on-chip cores exposes the energy and area …

Much of the complexity and overhead (directory, state bits, invalidations) of a typical
directory coherence implementation stems from the effort to make it" invisible" even to the …

With the trend towards increasing number of processor cores in future chip architectures,
scalable directory-based protocols for maintaining cache coherence will be needed …

Abstract System and methods for cache coherence in a multi-core processing environment
having a local/shared cache hierarchy. The system includes multiple processor cores, a …

Programming for parallel architectures that do not have a shared address space is extremely
difficult due to the need for explicit communication between memories of different compute …

Cache misses for which data must be obtained from a remote cache (cache-to-cache
transfer misses) account for an important fraction of the total miss rate. Unfortunately, cc …

One important issue the designer of a scalable shared-memory multiprocessor must deal
with is the amount of extra memory required to store the directory information. It is desirable …

This paper presents the Distributed Cooperative Caching, a scalable and energy-efficient
scheme to manage chip multiprocessor (CMP) cache resources. The proposed configuration …

As more processing cores are integrated into one chip and feature size continues to shrink,
the average access latency for remote nodes using directory-based coherence protocol …

Load instructions often limit instruction-level parallelism (ILP) in modern processors due to
data and resource dependences they cause. Prior techniques like Load Value Prediction …