Programmable All-in-One 4x8-/2x16-/1x32-bits Dual Mode Logic Multiplier in 16 nm FinFET with Semi-Automatic Flow

N Shavit, I Stanger, R Taco, A Fish, I Levi - IEEE Access, 2023 - ieeexplore.ieee.org
In this paper, an improved multiplier architecture, utilizing dual mode logic (DML) targeting
single-instruction-multiple-data (SIMD)-like systems is proposed. The design introduces …

Energy-Aware Register Allocation for VLIW Processors

F Stuckmann, M Weißbrich, G Payá-Vayá - Journal of Signal Processing …, 2024 - Springer
The efficiency of VLIW processors can be improved by reducing the energy consumption
associated with accessing the register-file. This paper presents an energy-aware register …

Multi-Ported GC-eDRAM Bitcell with Dynamic Port Configuration and Refresh Mechanism

R Golman, R Giterman, A Teman - Journal of Low Power Electronics and …, 2024 - mdpi.com
Embedded memories occupy an increasingly dominant part of the area and power budgets
of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by …

Selfie5: An Autonomous, Self-Contained Verification Approach for High-Throughput Random Testing of Programmable Processors

Y Kra, N Kra, A Teman - 2024 Design, Automation & Test in …, 2024 - ieeexplore.ieee.org
Random testing plays a crucial role in processor designs, complementing other verification
methodologies. This paper introduces Selfie5, an autonomous, self-contained verification …

A 4T GC-eDRAM Bitcell with Differential Readout Mechanism For High Performance Applications

R Golman, A Segev, A Teman - 2024 19th Conference on Ph …, 2024 - ieeexplore.ieee.org
Gain-cell embedded DRAM (GC-eDRAM) is a dense, low power option for embedded
memory implementation, supporting low supply voltages. However, due to its structure, the …