Van der Waals polarity-engineered 3D integration of 2D complementary logic

Y Guo, J Li, X Zhan, C Wang, M Li, B Zhang, Z Wang… - Nature, 2024 - nature.com
Vertical three-dimensional integration of two-dimensional (2D) semiconductors holds great
promise, as it offers the possibility to scale up logic layers in the z axis,–. Indeed, vertical …

There's Not Enough Room at the Bottom

ZV HAN - communities.springernature.com
Background In the past decades, Si FETs shrank their lateral sizes continuously, following
the famed Moore's law [1]. The footprint of a single transistor has been scaled from a few …