Gate length controlled vertical FETs
A semiconductor structure and a method a method of forming a vertical FET (Field-Effect
Transistor), includes growing a bottom source-drain layer of a second type on a substrate of …
Transistor), includes growing a bottom source-drain layer of a second type on a substrate of …
Methods of forming a gate structure on a vertical transistor device
JH Zhang, SJ Bentley, KY Lim - US Patent 9,799,751, 2017 - Google Patents
US9799751B1 - Methods of forming a gate structure on a vertical transistor device - Google
Patents US9799751B1 - Methods of forming a gate structure on a vertical transistor device …
Patents US9799751B1 - Methods of forming a gate structure on a vertical transistor device …
Vertical FET with reduced parasitic capacitance
K Cheng, X Miao, PJ Oldiges, XU Wenyu… - US Patent …, 2017 - Google Patents
(57) ABSTRACT A method for reducing parasitic capacitance of a semicon ductor structure
is provided. The method includes forming a fin structure over a substrate, forming a first …
is provided. The method includes forming a fin structure over a substrate, forming a first …
Self-aligned source/drain junction for vertical field-effect transistor (FET) and method of forming the same
(57) ABSTRACT A method for manufacturing a semiconductor device includes forming a
bottom source/drain region on a sub strate, forming a semiconductor layer on the bottom …
bottom source/drain region on a sub strate, forming a semiconductor layer on the bottom …
Precise junction placement in vertical semiconductor devices using etch stop layers
H Bu, L Jiang, SO Koswatta, J Wang - US Patent 9,954,101, 2018 - Google Patents
A semiconductor device is provided that includes a first of a source region and a drain
region comprised of a first semiconductor material, wherein an etch stop layer of a second …
region comprised of a first semiconductor material, wherein an etch stop layer of a second …
Vertical field-effect transistor having a dielectric spacer between a gate electrode edge and a self-aligned source/drain contact
H Zang, H Huang - US Patent 10,211,315, 2019 - Google Patents
Structures for a vertical-transport field-effect transistor and methods for forming a structure for
a vertical-transport field-effect transistor. A semiconductor fin is formed on a source/drain …
a vertical-transport field-effect transistor. A semiconductor fin is formed on a source/drain …
Vertical transistors with different gate lengths
Techniques for forming VFETs with differing gate lengths are provided. In one aspect, a
method for forming a VFET device includes: patterning fins in a substrate, wherein at least …
method for forming a VFET device includes: patterning fins in a substrate, wherein at least …
Vertical fin field effect transistor devices with self-aligned source and drain junctions
K Cheng, J Li, CH Lee, S Mochizuki - US Patent 10,600,885, 2020 - Google Patents
A method of forming a fin field effect transistor device is provided. The method includes
forming a plurality of vertical fins on a substrate. The method further includes forming a …
forming a plurality of vertical fins on a substrate. The method further includes forming a …
Method of forming improved vertical FET process with controlled gate length and self-aligned junctions
T Yamashita, C Zhang - US Patent 10,396,178, 2019 - Google Patents
Method and structure of forming a vertical FET. The method includes depositing a bottom
source-drain layer over a substrate; depositing a first heterostructure layer over the bottom …
source-drain layer over a substrate; depositing a first heterostructure layer over the bottom …
Super long channel device within VFET architecture
MA Bergendahl, K Cheng, G Karve, FL Lie… - US Patent …, 2020 - Google Patents
Embodiments of the present invention are directed to a method for fabricating a
semiconductor device. A nonlimiting example of the method includes forming a pair of …
semiconductor device. A nonlimiting example of the method includes forming a pair of …