Statistical modeling and simulation of threshold variation under random dopant fluctuations and line-edge roughness
The threshold voltage (V th) of a nanoscale transistor is severely affected by random dopant
fluctuations and line-edge roughness. The analysis of these effects usually requires …
fluctuations and line-edge roughness. The analysis of these effects usually requires …
Variability in nanometer CMOS: Impact, analysis, and minimization
D Sylvester, K Agarwal, S Shah - Integration, 2008 - Elsevier
Variation is a significant concern in nanometer-scale CMOS due to manufacturing
equipment being pushed to fundamental limits, particularly in lithography. In this paper, we …
equipment being pushed to fundamental limits, particularly in lithography. In this paper, we …
From poly line to transistor: building BSIM models for non-rectangular transistors
WJ Poppe, L Capodieci, J Wu… - Design and Process …, 2006 - spiedigitallibrary.org
Non-rectangular transistors in today's advanced processes pose a potential problem
between manufacturing and design as today's compact transistor models have only one …
between manufacturing and design as today's compact transistor models have only one …
[图书][B] Nano-CMOS Design for Manufacturability: Robust Circuit and Physical Design for Sub-65nm Technology Nodes
BP Wong, A Mittal, GW Starr, F Zach, V Moroz, A Kahng - 2008 - books.google.com
Discover innovative tools that pave the way from circuit and physical design to fabrication
processing Nano-CMOS Design for Manufacturability examines the challenges that design …
processing Nano-CMOS Design for Manufacturability examines the challenges that design …
Statistical modeling and simulation of threshold variation under dopant fluctuations and line-edge roughness
The threshold voltage (Vth) of a nanoscale transistor is severely affected by random dopant
fluctuations and line-edge roughness. The analysis of these effects usually requires …
fluctuations and line-edge roughness. The analysis of these effects usually requires …
Modeling and analysis of non-rectangular gate for post-lithography circuit simulation
In the nano regime it has become increasingly important to consider the impact of non-
rectangular gate (NRG) shape caused due to sub-wavelength lithography. NRG dramatically …
rectangular gate (NRG) shape caused due to sub-wavelength lithography. NRG dramatically …
Impact of guardband reduction on design outcomes: A quantitative approach
The value of guardband reduction is a critical open issue for the semiconductor industry. For
example, due to competitive pressure, foundries have started to incent the design of …
example, due to competitive pressure, foundries have started to incent the design of …
[图书][B] Nanoscale CMOS VLSI circuits: design for manufacturability
S Kundu, A Sreedhar - 2010 - dl.acm.org
Cutting-edge Design for Manufacturability Techniques for Nanoscale CMOS VLSI Circuits
Covering defect analysis, equipment, and lithographic control evaluations, this book offers a …
Covering defect analysis, equipment, and lithographic control evaluations, this book offers a …
Lithography simulation-based full-chip design analyses
Today's design flows sign-off performance and power prior to application of resolution
enhancement techniques (RETs). Together with process variations, RETs can lead to …
enhancement techniques (RETs). Together with process variations, RETs can lead to …
Electrically driven optical proximity correction based on linear programming
S Banerjee, P Elakkumanan… - 2008 IEEE/ACM …, 2008 - ieeexplore.ieee.org
Conventional optical proximity correction (OPC) tools aim to minimize edge placement
errors (EPE) due to the optical and resist process by moving mask edges. However, in low …
errors (EPE) due to the optical and resist process by moving mask edges. However, in low …